Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 1 | /* |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, Arm Limited. All rights reserved. |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 7 | #include <arch.h> |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 8 | #include <asm_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 9 | #include <common/bl_common.h> |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 10 | #include <cortex_a76ae.h> |
| 11 | #include <cpu_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 12 | #include "wa_cve_2022_23960_bhb_vector.S" |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 13 | |
John Tsichritzis | fe6df39 | 2019-03-19 17:20:52 +0000 | [diff] [blame] | 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
John Tsichritzis | 7557c66 | 2019-06-03 13:54:30 +0100 | [diff] [blame] | 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 24 | #if WORKAROUND_CVE_2022_23960 |
| 25 | wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae |
| 26 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 27 | |
| 28 | func check_errata_cve_2022_23960 |
| 29 | #if WORKAROUND_CVE_2022_23960 |
| 30 | mov x0, #ERRATA_APPLIES |
| 31 | #else |
| 32 | mov x0, #ERRATA_MISSING |
| 33 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 34 | ret |
| 35 | endfunc check_errata_cve_2022_23960 |
| 36 | |
| 37 | /* -------------------------------------------- |
| 38 | * The CPU Ops reset function for Cortex-A76AE. |
| 39 | * Shall clobber: x0-x19 |
| 40 | * -------------------------------------------- |
| 41 | */ |
| 42 | func cortex_a76ae_reset_func |
| 43 | #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 |
| 44 | /* |
| 45 | * The Cortex-A76ae generic vectors are overridden to apply errata |
| 46 | * mitigation on exception entry from lower ELs. |
| 47 | */ |
| 48 | adr x0, wa_cve_vbar_cortex_a76ae |
| 49 | msr vbar_el3, x0 |
| 50 | isb |
| 51 | #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ |
| 52 | |
| 53 | ret |
| 54 | endfunc cortex_a76ae_reset_func |
| 55 | |
| 56 | /* ---------------------------------------------------- |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 57 | * HW will do the cache maintenance while powering down |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 58 | * ---------------------------------------------------- |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 59 | */ |
| 60 | func cortex_a76ae_core_pwr_dwn |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 61 | /* --------------------------------------------------- |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 62 | * Enable CPU power down bit in power control register |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 63 | * --------------------------------------------------- |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 64 | */ |
| 65 | mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1 |
| 66 | orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK |
| 67 | msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0 |
| 68 | isb |
| 69 | ret |
| 70 | endfunc cortex_a76ae_core_pwr_dwn |
| 71 | |
| 72 | #if REPORT_ERRATA |
| 73 | /* |
| 74 | * Errata printing function for Cortex-A76AE. Must follow AAPCS. |
| 75 | */ |
| 76 | func cortex_a76ae_errata_report |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 77 | stp x8, x30, [sp, #-16]! |
| 78 | |
| 79 | bl cpu_get_rev_var |
| 80 | mov x8, x0 |
| 81 | |
| 82 | /* |
| 83 | * Report all errata. The revision-variant information is passed to |
| 84 | * checking functions of each errata. |
| 85 | */ |
| 86 | report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960 |
| 87 | |
| 88 | ldp x8, x30, [sp], #16 |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 89 | ret |
| 90 | endfunc cortex_a76ae_errata_report |
| 91 | #endif /* REPORT_ERRATA */ |
| 92 | |
| 93 | /* --------------------------------------------- |
| 94 | * This function provides cortex_a76ae specific |
| 95 | * register information for crash reporting. |
| 96 | * It needs to return with x6 pointing to |
| 97 | * a list of register names in ascii and |
| 98 | * x8 - x15 having values of registers to be |
| 99 | * reported. |
| 100 | * --------------------------------------------- |
| 101 | */ |
| 102 | .section .rodata.cortex_a76ae_regs, "aS" |
| 103 | cortex_a76ae_regs: /* The ASCII list of register names to be reported */ |
| 104 | .asciz "cpuectlr_el1", "" |
| 105 | |
| 106 | func cortex_a76ae_cpu_reg_dump |
| 107 | adr x6, cortex_a76ae_regs |
| 108 | mrs x8, CORTEX_A76AE_CPUECTLR_EL1 |
| 109 | ret |
| 110 | endfunc cortex_a76ae_cpu_reg_dump |
| 111 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 112 | declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \ |
Alexei Fedorov | 4800943 | 2019-04-04 16:26:34 +0100 | [diff] [blame] | 113 | cortex_a76ae_core_pwr_dwn |