blob: 3404d313b79f24bfe0b2ae8db4bddae96bfae148 [file] [log] [blame]
Chengci Xudb1e75b2022-07-20 16:20:15 +08001/*
2 * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef IOMMU_PRIV_H
8#define IOMMU_PRIV_H
9
10#include <common/debug.h>
11#include <lib/mmio.h>
12#include <mtk_sip_svc.h>
13
14#define LARB_CFG_ENTRY(bs, p_nr, dom) \
15 { .base = (bs), .port_nr = (p_nr), \
16 .dom_id = (dom), .to_sram = 0, }
17
18#define LARB_CFG_ENTRY_WITH_PATH(bs, p_nr, dom, sram) \
19 { .base = (bs), .port_nr = (p_nr), \
20 .dom_id = (dom), .to_sram = (sram), }
21
22#define IFR_MST_CFG_ENTRY(idx, bit) \
23 { .cfg_addr_idx = (idx), .r_mmu_en_bit = (bit), }
24
25enum IOMMU_ATF_CMD {
26 IOMMU_ATF_CMD_CONFIG_SMI_LARB, /* For mm master to enable iommu */
27 IOMMU_ATF_CMD_CONFIG_INFRA_IOMMU, /* For infra master to enable iommu */
28 IOMMU_ATF_CMD_COUNT,
29};
30
31struct mtk_smi_larb_config {
32 uint32_t base;
33 uint32_t port_nr;
34 uint32_t dom_id;
35 uint32_t to_sram;
36 uint32_t sec_en_msk;
37};
38
39struct mtk_ifr_mst_config {
40 uint8_t cfg_addr_idx;
41 uint8_t r_mmu_en_bit;
42};
43
44#endif /* IOMMU_PRIV_H */