| Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 1 | /* |
| Antonio Nino Diaz | 6942f05 | 2018-07-14 02:15:51 +0100 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
| Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __RPI3_HW__ |
| 8 | #define __RPI3_HW__ |
| 9 | |
| 10 | #include <utils_def.h> |
| 11 | |
| 12 | /* |
| 13 | * Peripherals |
| 14 | */ |
| 15 | |
| 16 | #define RPI3_IO_BASE ULL(0x3F000000) |
| 17 | #define RPI3_IO_SIZE ULL(0x01000000) |
| 18 | |
| 19 | /* |
| Antonio Nino Diaz | ecf3471 | 2018-07-12 13:38:53 +0100 | [diff] [blame] | 20 | * ARM <-> VideoCore mailboxes |
| 21 | */ |
| 22 | #define RPI3_MBOX_OFFSET ULL(0x0000B880) |
| 23 | #define RPI3_MBOX_BASE (RPI3_IO_BASE + RPI3_MBOX_OFFSET) |
| 24 | /* VideoCore -> ARM */ |
| 25 | #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000) |
| 26 | #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010) |
| 27 | #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014) |
| 28 | #define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018) |
| 29 | #define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C) |
| 30 | /* ARM -> VideoCore */ |
| 31 | #define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020) |
| 32 | #define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030) |
| 33 | #define RPI3_MBOX1_SENDER_OFFSET ULL(0x00000034) |
| 34 | #define RPI3_MBOX1_STATUS_OFFSET ULL(0x00000038) |
| 35 | #define RPI3_MBOX1_CONFIG_OFFSET ULL(0x0000003C) |
| 36 | /* Mailbox status constants */ |
| 37 | #define RPI3_MBOX_STATUS_FULL_MASK U(0x80000000) /* Set if full */ |
| 38 | #define RPI3_MBOX_STATUS_EMPTY_MASK U(0x40000000) /* Set if empty */ |
| 39 | |
| 40 | /* |
| Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 41 | * Power management, reset controller, watchdog. |
| 42 | */ |
| 43 | #define RPI3_IO_PM_OFFSET ULL(0x00100000) |
| 44 | #define RPI3_PM_BASE (RPI3_IO_BASE + RPI3_IO_PM_OFFSET) |
| 45 | /* Registers on top of RPI3_PM_BASE. */ |
| 46 | #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C) |
| Antonio Nino Diaz | 6942f05 | 2018-07-14 02:15:51 +0100 | [diff] [blame] | 47 | #define RPI3_PM_RSTS_OFFSET ULL(0x00000020) |
| Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 48 | #define RPI3_PM_WDOG_OFFSET ULL(0x00000024) |
| 49 | /* Watchdog constants */ |
| Antonio Nino Diaz | 6942f05 | 2018-07-14 02:15:51 +0100 | [diff] [blame] | 50 | #define RPI3_PM_PASSWORD U(0x5A000000) |
| 51 | #define RPI3_PM_RSTC_WRCFG_MASK U(0x00000030) |
| 52 | #define RPI3_PM_RSTC_WRCFG_FULL_RESET U(0x00000020) |
| 53 | /* |
| 54 | * The RSTS register is used by the VideoCore firmware when booting the |
| 55 | * Raspberry Pi to know which partition to boot from. The partition value is |
| 56 | * formed by bits 0, 2, 4, 6, 8 and 10. Partition 63 is used by said firmware |
| 57 | * to indicate halt. |
| 58 | */ |
| 59 | #define RPI3_PM_RSTS_WRCFG_HALT U(0x00000555) |
| 60 | |
| 61 | /* |
| 62 | * Serial port (called 'Mini UART' in the BCM docucmentation). |
| 63 | */ |
| 64 | #define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040) |
| 65 | #define RPI3_MINI_UART_BASE (RPI3_IO_BASE + RPI3_IO_MINI_UART_OFFSET) |
| 66 | #define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000) |
| Antonio Nino Diaz | ae6779e | 2017-11-06 14:49:04 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
| 69 | * Local interrupt controller |
| 70 | */ |
| 71 | #define RPI3_INTC_BASE_ADDRESS ULL(0x40000000) |
| 72 | /* Registers on top of RPI3_INTC_BASE_ADDRESS */ |
| 73 | #define RPI3_INTC_CONTROL_OFFSET ULL(0x00000000) |
| 74 | #define RPI3_INTC_PRESCALER_OFFSET ULL(0x00000008) |
| 75 | #define RPI3_INTC_MBOX_CONTROL_OFFSET ULL(0x00000050) |
| 76 | #define RPI3_INTC_MBOX_CONTROL_SLOT3_FIQ ULL(0x00000080) |
| 77 | #define RPI3_INTC_PENDING_FIQ_OFFSET ULL(0x00000070) |
| 78 | #define RPI3_INTC_PENDING_FIQ_MBOX3 ULL(0x00000080) |
| 79 | |
| 80 | #endif /* __RPI3_HW__ */ |