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Soby Mathew44170c42016-03-22 15:51:08 +00001/*
Antonio Nino Diazb9ae5db2018-05-02 11:23:56 +01002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathew44170c42016-03-22 15:51:08 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew44170c42016-03-22 15:51:08 +00005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
Antonio Nino Diazd1beee22016-12-13 15:28:54 +000010#include <bl_common.h>
Antonio Nino Diazd1beee22016-12-13 15:28:54 +000011#include <common_def.h>
Soby Mathew44170c42016-03-22 15:51:08 +000012#include <platform_def.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010013#include <stdint.h>
Sandrine Bailleux7659a262016-07-05 09:55:03 +010014#include <utils.h>
Soby Mathew44170c42016-03-22 15:51:08 +000015#include <xlat_tables.h>
Sandrine Bailleux090c8492017-05-19 09:59:37 +010016#include <xlat_tables_arch.h>
Soby Mathew44170c42016-03-22 15:51:08 +000017#include "../xlat_tables_private.h"
18
Sandrine Bailleux090c8492017-05-19 09:59:37 +010019#define XLAT_TABLE_LEVEL_BASE \
20 GET_XLAT_TABLE_LEVEL_BASE(PLAT_VIRT_ADDR_SPACE_SIZE)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +010021
Sandrine Bailleux090c8492017-05-19 09:59:37 +010022#define NUM_BASE_LEVEL_ENTRIES \
23 GET_NUM_BASE_LEVEL_ENTRIES(PLAT_VIRT_ADDR_SPACE_SIZE)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +010024
25static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
26 __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
Soby Mathew44170c42016-03-22 15:51:08 +000027
28static unsigned long long tcr_ps_bits;
29
30static unsigned long long calc_physical_addr_size_bits(
31 unsigned long long max_addr)
32{
33 /* Physical address can't exceed 48 bits */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010034 assert((max_addr & ADDR_MASK_48_TO_63) == 0U);
Soby Mathew44170c42016-03-22 15:51:08 +000035
36 /* 48 bits address */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010037 if ((max_addr & ADDR_MASK_44_TO_47) != 0U)
Soby Mathew44170c42016-03-22 15:51:08 +000038 return TCR_PS_BITS_256TB;
39
40 /* 44 bits address */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010041 if ((max_addr & ADDR_MASK_42_TO_43) != 0U)
Soby Mathew44170c42016-03-22 15:51:08 +000042 return TCR_PS_BITS_16TB;
43
44 /* 42 bits address */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010045 if ((max_addr & ADDR_MASK_40_TO_41) != 0U)
Soby Mathew44170c42016-03-22 15:51:08 +000046 return TCR_PS_BITS_4TB;
47
48 /* 40 bits address */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010049 if ((max_addr & ADDR_MASK_36_TO_39) != 0U)
Soby Mathew44170c42016-03-22 15:51:08 +000050 return TCR_PS_BITS_1TB;
51
52 /* 36 bits address */
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010053 if ((max_addr & ADDR_MASK_32_TO_35) != 0U)
Soby Mathew44170c42016-03-22 15:51:08 +000054 return TCR_PS_BITS_64GB;
55
56 return TCR_PS_BITS_4GB;
57}
58
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +000059#if ENABLE_ASSERTIONS
Antonio Nino Diazb9ae5db2018-05-02 11:23:56 +010060/*
61 * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is
62 * supported in ARMv8.2 onwards.
63 */
Antonio Nino Diazd1beee22016-12-13 15:28:54 +000064static const unsigned int pa_range_bits_arr[] = {
65 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
Antonio Nino Diazb9ae5db2018-05-02 11:23:56 +010066 PARANGE_0101, PARANGE_0110
Antonio Nino Diazd1beee22016-12-13 15:28:54 +000067};
68
69static unsigned long long get_max_supported_pa(void)
70{
71 u_register_t pa_range = read_id_aa64mmfr0_el1() &
72 ID_AA64MMFR0_EL1_PARANGE_MASK;
73
74 /* All other values are reserved */
75 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
76
77 return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
78}
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +000079#endif /* ENABLE_ASSERTIONS */
Antonio Nino Diazd1beee22016-12-13 15:28:54 +000080
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010081unsigned int xlat_arch_current_el(void)
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010082{
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010083 unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010084
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010085 assert(el > 0U);
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010086
87 return el;
88}
89
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010090uint64_t xlat_arch_get_xn_desc(unsigned int el)
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010091{
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010092 if (el == 3U) {
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010093 return UPPER_ATTRS(XN);
94 } else {
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010095 assert(el == 1U);
Antonio Nino Diazefabaa92017-04-27 13:30:22 +010096 return UPPER_ATTRS(PXN);
97 }
98}
99
Soby Mathew44170c42016-03-22 15:51:08 +0000100void init_xlat_tables(void)
101{
102 unsigned long long max_pa;
103 uintptr_t max_va;
104 print_mmap();
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100105 init_xlation_table(0U, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100106 &max_va, &max_pa);
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000107
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100108 assert(max_va <= (PLAT_VIRT_ADDR_SPACE_SIZE - 1U));
109 assert(max_pa <= (PLAT_PHY_ADDR_SPACE_SIZE - 1U));
110 assert((PLAT_PHY_ADDR_SPACE_SIZE - 1U) <= get_max_supported_pa());
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000111
Soby Mathew44170c42016-03-22 15:51:08 +0000112 tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
Soby Mathew44170c42016-03-22 15:51:08 +0000113}
114
115/*******************************************************************************
116 * Macro generating the code for the function enabling the MMU in the given
117 * exception level, assuming that the pagetables have already been created.
118 *
119 * _el: Exception level at which the function will run
120 * _tcr_extra: Extra bits to set in the TCR register. This mask will
121 * be OR'ed with the default TCR value.
122 * _tlbi_fct: Function to invalidate the TLBs at the current
123 * exception level
124 ******************************************************************************/
125#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
126 void enable_mmu_el##_el(unsigned int flags) \
127 { \
128 uint64_t mair, tcr, ttbr; \
129 uint32_t sctlr; \
130 \
131 assert(IS_IN_EL(_el)); \
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100132 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0U); \
Soby Mathew44170c42016-03-22 15:51:08 +0000133 \
134 /* Set attributes in the right indices of the MAIR */ \
135 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
136 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
137 ATTR_IWBWA_OWBWA_NTR_INDEX); \
138 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
139 ATTR_NON_CACHEABLE_INDEX); \
140 write_mair_el##_el(mair); \
141 \
142 /* Invalidate TLBs at the current exception level */ \
143 _tlbi_fct(); \
144 \
145 /* Set TCR bits as well. */ \
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100146 /* Set T0SZ to (64 - width of virtual address space) */ \
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100147 int t0sz = 64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE);\
148 \
149 if ((flags & XLAT_TABLE_NC) != 0U) { \
Summer Qindaf5dbb2017-03-16 17:16:34 +0000150 /* Inner & outer non-cacheable non-shareable. */\
151 tcr = TCR_SH_NON_SHAREABLE | \
152 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100153 (uint64_t) t0sz; \
Summer Qindaf5dbb2017-03-16 17:16:34 +0000154 } else { \
155 /* Inner & outer WBWA & shareable. */ \
156 tcr = TCR_SH_INNER_SHAREABLE | \
157 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100158 (uint64_t) t0sz; \
Summer Qindaf5dbb2017-03-16 17:16:34 +0000159 } \
Soby Mathew44170c42016-03-22 15:51:08 +0000160 tcr |= _tcr_extra; \
161 write_tcr_el##_el(tcr); \
162 \
163 /* Set TTBR bits as well */ \
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100164 ttbr = (uint64_t) base_xlation_table; \
Soby Mathew44170c42016-03-22 15:51:08 +0000165 write_ttbr0_el##_el(ttbr); \
166 \
167 /* Ensure all translation table writes have drained */ \
168 /* into memory, the TLB invalidation is complete, */ \
169 /* and translation register writes are committed */ \
170 /* before enabling the MMU */ \
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000171 dsbish(); \
Soby Mathew44170c42016-03-22 15:51:08 +0000172 isb(); \
173 \
174 sctlr = read_sctlr_el##_el(); \
175 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
176 \
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +0100177 if ((flags & DISABLE_DCACHE) != 0U) \
Soby Mathew44170c42016-03-22 15:51:08 +0000178 sctlr &= ~SCTLR_C_BIT; \
179 else \
180 sctlr |= SCTLR_C_BIT; \
181 \
182 write_sctlr_el##_el(sctlr); \
183 \
184 /* Ensure the MMU enable takes effect immediately */ \
185 isb(); \
Jeenu Viswambharan9f142612018-04-27 15:06:57 +0100186 } \
187 \
188 void enable_mmu_direct_el##_el(unsigned int flags) \
189 { \
190 enable_mmu_el##_el(flags); \
Soby Mathew44170c42016-03-22 15:51:08 +0000191 }
192
193/* Define EL1 and EL3 variants of the function enabling the MMU */
194DEFINE_ENABLE_MMU_EL(1,
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100195 /*
196 * TCR_EL1.EPD1: Disable translation table walk for addresses
197 * that are translated using TTBR1_EL1.
198 */
199 TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT),
Soby Mathew44170c42016-03-22 15:51:08 +0000200 tlbivmalle1)
201DEFINE_ENABLE_MMU_EL(3,
202 TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
203 tlbialle3)