Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 7 | #ifndef PLATFORM_DEF_H |
| 8 | #define PLATFORM_DEF_H |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 9 | |
| 10 | #include <arm_def.h> |
Sughosh Ganu | 79b91d4 | 2018-05-16 15:13:25 +0530 | [diff] [blame] | 11 | #include <arm_spm_def.h> |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 12 | #include <board_arm_def.h> |
| 13 | #include <board_css_def.h> |
| 14 | #include <common_def.h> |
| 15 | #include <css_def.h> |
| 16 | #include <soc_css_def.h> |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 17 | #include <utils_def.h> |
Sughosh Ganu | 70661cf | 2018-05-16 17:26:40 +0530 | [diff] [blame] | 18 | #include <xlat_tables_defs.h> |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 19 | |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 20 | #define CSS_SGI_MAX_CPUS_PER_CLUSTER 4 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 21 | |
| 22 | /* CPU topology */ |
| 23 | #define PLAT_ARM_CLUSTER_COUNT 2 |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 24 | #define CSS_SGI_MAX_PE_PER_CPU 1 |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 25 | #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ |
Vishwanatha HG | 64f0b6f | 2018-05-08 17:15:37 +0530 | [diff] [blame] | 26 | CSS_SGI_MAX_CPUS_PER_CLUSTER * \ |
| 27 | CSS_SGI_MAX_PE_PER_CPU) |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 28 | |
| 29 | #if ARM_BOARD_OPTIMISE_MEM |
| 30 | |
| 31 | #if defined(IMAGE_BL31) || defined(IMAGE_BL32) |
| 32 | # define PLAT_ARM_MMAP_ENTRIES 6 |
| 33 | # define MAX_XLAT_TABLES 4 |
| 34 | #else |
| 35 | # define PLAT_ARM_MMAP_ENTRIES 10 |
| 36 | # define MAX_XLAT_TABLES 5 |
| 37 | #endif |
| 38 | |
| 39 | #if TRUSTED_BOARD_BOOT |
| 40 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 |
| 41 | #else |
| 42 | # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 |
| 43 | #endif |
| 44 | |
| 45 | #if TRUSTED_BOARD_BOOT |
| 46 | # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 |
| 47 | #else |
| 48 | # define PLAT_ARM_MAX_BL2_SIZE 0xC000 |
| 49 | #endif |
| 50 | |
| 51 | #endif /* ARM_BOARD_OPTIMISE_MEM */ |
| 52 | |
| 53 | #define PLAT_ARM_NSTIMER_FRAME_ID 0 |
| 54 | |
| 55 | #define PLAT_CSS_MHU_BASE 0x45000000 |
| 56 | |
| 57 | #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 |
| 58 | #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ |
| 59 | |
Chris Kay | 42fbdfc | 2018-05-10 14:27:45 +0100 | [diff] [blame] | 60 | #define PLAT_ARM_NSRAM_BASE 0x06000000 |
| 61 | #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ |
| 62 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 63 | #define PLAT_MAX_PWR_LVL U(1) |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 64 | |
| 65 | #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ |
| 66 | CSS_IRQ_MHU |
| 67 | |
| 68 | #define PLAT_ARM_G0_IRQS ARM_G0_IRQS |
| 69 | |
| 70 | #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) |
| 71 | #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) |
| 72 | |
| 73 | #define CSS_SGI_DEVICE_BASE (0x20000000) |
| 74 | #define CSS_SGI_DEVICE_SIZE (0x20000000) |
| 75 | #define CSS_SGI_MAP_DEVICE MAP_REGION_FLAT( \ |
| 76 | CSS_SGI_DEVICE_BASE, \ |
| 77 | CSS_SGI_DEVICE_SIZE, \ |
| 78 | MT_DEVICE | MT_RW | MT_SECURE) |
| 79 | |
| 80 | #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 |
| 81 | #define SGI_BOOT_CFG_ADDR 0x45410000 |
| 82 | #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 |
| 83 | #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 6 |
| 84 | |
| 85 | /* GIC related constants */ |
| 86 | #define PLAT_ARM_GICD_BASE 0x30000000 |
| 87 | #define PLAT_ARM_GICC_BASE 0x2C000000 |
| 88 | #define PLAT_ARM_GICR_BASE 0x300C0000 |
| 89 | |
Sughosh Ganu | e1579e0 | 2018-05-16 17:19:56 +0530 | [diff] [blame] | 90 | /* Map the secure region for access from S-EL0 */ |
| 91 | #define PLAT_ARM_SECURE_MAP_DEVICE MAP_REGION_FLAT( \ |
| 92 | SOC_CSS_DEVICE_BASE, \ |
| 93 | SOC_CSS_DEVICE_SIZE, \ |
| 94 | MT_DEVICE | MT_RW | MT_SECURE | MT_USER) |
| 95 | |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 96 | #if RAS_EXTENSION |
| 97 | /* Allocate 128KB for CPER buffers */ |
Sughosh Ganu | 70661cf | 2018-05-16 17:26:40 +0530 | [diff] [blame] | 98 | #define PLAT_SP_BUF_BASE ULL(0x20000) |
| 99 | |
| 100 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ |
| 101 | ARM_SP_IMAGE_NS_BUF_SIZE + \ |
| 102 | PLAT_SP_BUF_BASE) |
| 103 | |
| 104 | /* Platform specific SMC FID's used for RAS */ |
| 105 | #define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042 |
| 106 | #define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042 |
| 107 | |
| 108 | #define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043 |
| 109 | #define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043 |
| 110 | |
| 111 | #define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044 |
| 112 | #define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044 |
| 113 | |
| 114 | /* ARM SDEI dynamic shared event numbers */ |
| 115 | #define SGI_SDEI_DS_EVENT_0 804 |
| 116 | #define SGI_SDEI_DS_EVENT_1 805 |
| 117 | |
| 118 | #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ |
| 119 | SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ |
| 120 | SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \ |
| 121 | SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL), |
| 122 | #define PLAT_ARM_SHARED_SDEI_EVENTS |
| 123 | |
| 124 | #define ARM_SP_CPER_BUF_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ |
| 125 | ARM_SP_IMAGE_NS_BUF_SIZE) |
| 126 | #define ARM_SP_CPER_BUF_SIZE ULL(0x20000) |
| 127 | #define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \ |
| 128 | ARM_SP_CPER_BUF_BASE, \ |
| 129 | ARM_SP_CPER_BUF_BASE, \ |
| 130 | ARM_SP_CPER_BUF_SIZE, \ |
| 131 | MT_RW_DATA | MT_NS | MT_USER, \ |
| 132 | PAGE_SIZE) |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 133 | |
Sughosh Ganu | 5f21294 | 2018-05-16 15:35:25 +0530 | [diff] [blame] | 134 | #else |
| 135 | #define PLAT_ARM_SP_IMAGE_STACK_BASE (ARM_SP_IMAGE_NS_BUF_BASE + \ |
| 136 | ARM_SP_IMAGE_NS_BUF_SIZE) |
| 137 | #endif /* RAS_EXTENSION */ |
| 138 | |
Nariman Poushin | 0ece80f | 2018-02-26 06:52:04 +0000 | [diff] [blame] | 139 | /* Platform ID address */ |
| 140 | #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) |
| 141 | #ifndef __ASSEMBLY__ |
| 142 | /* SSC_VERSION related accessors */ |
| 143 | /* Returns the part number of the platform */ |
| 144 | #define GET_SGI_PART_NUM \ |
| 145 | GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION)) |
| 146 | /* Returns the configuration number of the platform */ |
| 147 | #define GET_SGI_CONFIG_NUM \ |
| 148 | GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION)) |
| 149 | #endif /* __ASSEMBLY__ */ |
| 150 | |
Roberto Vargas | bcca6c6 | 2018-06-11 16:15:35 +0100 | [diff] [blame] | 151 | /******************************************************************************* |
| 152 | * Memprotect definitions |
| 153 | ******************************************************************************/ |
| 154 | /* PSCI memory protect definitions: |
| 155 | * This variable is stored in a non-secure flash because some ARM reference |
| 156 | * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT |
| 157 | * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. |
| 158 | */ |
| 159 | #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ |
| 160 | V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) |
| 161 | |
| 162 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 163 | #endif /* PLATFORM_DEF_H */ |