| Andre Przywara | 2d42e5f | 2020-11-28 01:39:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017-2020, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SUNXI_CPUCFG_H |
| 8 | #define SUNXI_CPUCFG_H |
| 9 | |
| 10 | #include <sunxi_mmap.h> |
| 11 | |
| 12 | /* c = cluster, n = core */ |
| 13 | #define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10) |
| 14 | #define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10) |
| 15 | #define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024) |
| 16 | #define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0) |
| 17 | |
| 18 | #define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4) |
| 19 | #define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8) |
| 20 | #define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8) |
| 21 | |
| 22 | #define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4) |
| 23 | #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4) |
| 24 | #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \ |
| 25 | (c) * 0x10 + (n) * 4) |
| 26 | |
| 27 | #define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100) |
| 28 | #define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104) |
| 29 | #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140) |
| 30 | #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144) |
| 31 | |
| Icenowy Zheng | 6f515d0 | 2021-07-22 09:35:19 +0800 | [diff] [blame] | 32 | #define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 |
| 33 | #define SUNXI_AA64nAA32_OFFSET 24 |
| 34 | |
| Andre Przywara | 2d42e5f | 2020-11-28 01:39:17 +0000 | [diff] [blame] | 35 | #endif /* SUNXI_CPUCFG_H */ |