developer | 6514957 | 2022-09-07 18:26:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef MT_SPM_INTERNAL_H |
| 8 | #define MT_SPM_INTERNAL_H |
| 9 | |
| 10 | #include <mt_spm.h> |
| 11 | |
| 12 | /* PCM_WDT_VAL */ |
| 13 | #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ |
| 14 | /* PCM_TIMER_VAL */ |
| 15 | #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) |
| 16 | |
| 17 | /* PCM_PWR_IO_EN */ |
| 18 | #define PCM_PWRIO_EN_R0 BIT(0) |
| 19 | #define PCM_PWRIO_EN_R7 BIT(7) |
| 20 | #define PCM_RF_SYNC_R0 BIT(16) |
| 21 | #define PCM_RF_SYNC_R6 BIT(22) |
| 22 | #define PCM_RF_SYNC_R7 BIT(23) |
| 23 | |
| 24 | /* SPM_SWINT */ |
| 25 | #define PCM_SW_INT0 BIT(0) |
| 26 | #define PCM_SW_INT1 BIT(1) |
| 27 | #define PCM_SW_INT2 BIT(2) |
| 28 | #define PCM_SW_INT3 BIT(3) |
| 29 | #define PCM_SW_INT4 BIT(4) |
| 30 | #define PCM_SW_INT5 BIT(5) |
| 31 | #define PCM_SW_INT6 BIT(6) |
| 32 | #define PCM_SW_INT7 BIT(7) |
| 33 | #define PCM_SW_INT8 BIT(8) |
| 34 | #define PCM_SW_INT9 BIT(9) |
| 35 | #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ |
| 36 | PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ |
| 37 | PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ |
| 38 | PCM_SW_INT0) |
| 39 | |
| 40 | /* SPM_AP_STANDBY_CON */ |
| 41 | #define WFI_OP_AND (1U) |
| 42 | #define WFI_OP_OR (0U) |
| 43 | |
| 44 | /* SPM_IRQ_MASK */ |
| 45 | #define ISRM_TWAM BIT(2) |
| 46 | #define ISRM_PCM_RETURN BIT(3) |
| 47 | #define ISRM_RET_IRQ0 BIT(8) |
| 48 | #define ISRM_RET_IRQ1 BIT(9) |
| 49 | #define ISRM_RET_IRQ2 BIT(10) |
| 50 | #define ISRM_RET_IRQ3 BIT(11) |
| 51 | #define ISRM_RET_IRQ4 BIT(12) |
| 52 | #define ISRM_RET_IRQ5 BIT(13) |
| 53 | #define ISRM_RET_IRQ6 BIT(14) |
| 54 | #define ISRM_RET_IRQ7 BIT(15) |
| 55 | #define ISRM_RET_IRQ8 BIT(16) |
| 56 | #define ISRM_RET_IRQ9 BIT(17) |
| 57 | #define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \ |
| 58 | (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \ |
| 59 | (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \ |
| 60 | (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \ |
| 61 | (ISRM_RET_IRQ1)) |
| 62 | #define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX |
| 63 | #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) |
| 64 | |
| 65 | /* SPM_IRQ_STA */ |
| 66 | #define ISRS_TWAM BIT(2) |
| 67 | #define ISRS_PCM_RETURN BIT(3) |
| 68 | #define ISRC_TWAM ISRS_TWAM |
| 69 | #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN |
| 70 | #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) |
| 71 | |
| 72 | /* SPM_WAKEUP_MISC */ |
| 73 | #define WAKE_MISC_GIC_WAKEUP (0x3FF) |
| 74 | #define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB |
| 75 | #define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB |
| 76 | #define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB |
| 77 | #define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB |
| 78 | #define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB |
| 79 | #define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB |
| 80 | #define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB |
| 81 | #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB |
| 82 | #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB |
| 83 | #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB |
| 84 | #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB |
| 85 | #define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB |
| 86 | #define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB |
| 87 | #define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB |
| 88 | |
| 89 | /* MD32PCM ADDR for SPM code fetch */ |
| 90 | #define MD32PCM_BASE (SPM_BASE + 0x0A00) |
| 91 | #define MD32PCM_CFGREG_SW_RSTN (MD32PCM_BASE + 0x0000) |
| 92 | #define MD32PCM_DMA0_SRC (MD32PCM_BASE + 0x0200) |
| 93 | #define MD32PCM_DMA0_DST (MD32PCM_BASE + 0x0204) |
| 94 | #define MD32PCM_DMA0_WPPT (MD32PCM_BASE + 0x0208) |
| 95 | #define MD32PCM_DMA0_WPTO (MD32PCM_BASE + 0x020C) |
| 96 | #define MD32PCM_DMA0_COUNT (MD32PCM_BASE + 0x0210) |
| 97 | #define MD32PCM_DMA0_CON (MD32PCM_BASE + 0x0214) |
| 98 | #define MD32PCM_DMA0_START (MD32PCM_BASE + 0x0218) |
| 99 | #define MD32PCM_DMA0_RLCT (MD32PCM_BASE + 0x0224) |
| 100 | #define MD32PCM_INTC_IRQ_RAW_STA (MD32PCM_BASE + 0x033C) |
| 101 | |
| 102 | /* ABORT MASK for DEBUG FOORTPRINT */ |
| 103 | #define DEBUG_ABORT_MASK (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \ |
| 104 | SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN) |
| 105 | |
| 106 | #define DEBUG_ABORT_MASK_1 (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \ |
| 107 | SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \ |
| 108 | SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \ |
| 109 | SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \ |
| 110 | SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \ |
| 111 | SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \ |
| 112 | SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT) |
| 113 | |
| 114 | #define MCUPM_MBOX_WAKEUP_CPU (0x0C55FD10) |
| 115 | |
| 116 | struct pcm_desc { |
| 117 | const char *version; /* PCM code version */ |
| 118 | uint32_t *base; /* binary array base */ |
| 119 | uintptr_t base_dma; /* dma addr of base */ |
| 120 | uint32_t pmem_words; |
| 121 | uint32_t total_words; |
| 122 | uint32_t pmem_start; |
| 123 | uint32_t dmem_start; |
| 124 | }; |
| 125 | |
| 126 | struct pwr_ctrl { |
| 127 | /* for SPM */ |
| 128 | uint32_t pcm_flags; |
| 129 | /* can override pcm_flags */ |
| 130 | uint32_t pcm_flags_cust; |
| 131 | /* set bit of pcm_flags, after pcm_flags_cust */ |
| 132 | uint32_t pcm_flags_cust_set; |
| 133 | /* clr bit of pcm_flags, after pcm_flags_cust */ |
| 134 | uint32_t pcm_flags_cust_clr; |
| 135 | uint32_t pcm_flags1; |
| 136 | /* can override pcm_flags1 */ |
| 137 | uint32_t pcm_flags1_cust; |
| 138 | /* set bit of pcm_flags1, after pcm_flags1_cust */ |
| 139 | uint32_t pcm_flags1_cust_set; |
| 140 | /* clr bit of pcm_flags1, after pcm_flags1_cust */ |
| 141 | uint32_t pcm_flags1_cust_clr; |
| 142 | /* @ 1T 32K */ |
| 143 | uint32_t timer_val; |
| 144 | /* @ 1T 32K, can override timer_val */ |
| 145 | uint32_t timer_val_cust; |
| 146 | /* stress for dpidle */ |
| 147 | uint32_t timer_val_ramp_en; |
| 148 | /* stress for suspend */ |
| 149 | uint32_t timer_val_ramp_en_sec; |
| 150 | uint32_t wake_src; |
| 151 | /* can override wake_src */ |
| 152 | uint32_t wake_src_cust; |
| 153 | /* disable wdt in suspend */ |
| 154 | uint8_t wdt_disable; |
| 155 | |
| 156 | /* SPM_AP_STANDBY_CON */ |
| 157 | /* [0] */ |
| 158 | uint8_t reg_wfi_op; |
| 159 | /* [1] */ |
| 160 | uint8_t reg_wfi_type; |
| 161 | /* [2] */ |
| 162 | uint8_t reg_mp0_cputop_idle_mask; |
| 163 | /* [3] */ |
| 164 | uint8_t reg_mp1_cputop_idle_mask; |
| 165 | /* [4] */ |
| 166 | uint8_t reg_mcusys_idle_mask; |
| 167 | /* [25] */ |
| 168 | uint8_t reg_md_apsrc_1_sel; |
| 169 | /* [26] */ |
| 170 | uint8_t reg_md_apsrc_0_sel; |
| 171 | /* [29] */ |
| 172 | uint8_t reg_conn_apsrc_sel; |
| 173 | |
| 174 | /* SPM_SRC_REQ */ |
| 175 | /* [0] */ |
| 176 | uint8_t reg_spm_apsrc_req; |
| 177 | /* [1] */ |
| 178 | uint8_t reg_spm_f26m_req; |
| 179 | /* [3] */ |
| 180 | uint8_t reg_spm_infra_req; |
| 181 | /* [4] */ |
| 182 | uint8_t reg_spm_vrf18_req; |
| 183 | /* [7] */ |
| 184 | uint8_t reg_spm_ddr_en_req; |
| 185 | /* [8] */ |
| 186 | uint8_t reg_spm_dvfs_req; |
| 187 | /* [9] */ |
| 188 | uint8_t reg_spm_sw_mailbox_req; |
| 189 | /* [10] */ |
| 190 | uint8_t reg_spm_sspm_mailbox_req; |
| 191 | /* [11] */ |
| 192 | uint8_t reg_spm_adsp_mailbox_req; |
| 193 | /* [12] */ |
| 194 | uint8_t reg_spm_scp_mailbox_req; |
| 195 | |
| 196 | /* SPM_SRC_MASK */ |
| 197 | /* [0] */ |
| 198 | uint8_t reg_sspm_srcclkena_0_mask_b; |
| 199 | /* [1] */ |
| 200 | uint8_t reg_sspm_infra_req_0_mask_b; |
| 201 | /* [2] */ |
| 202 | uint8_t reg_sspm_apsrc_req_0_mask_b; |
| 203 | /* [3] */ |
| 204 | uint8_t reg_sspm_vrf18_req_0_mask_b; |
| 205 | /* [4] */ |
| 206 | uint8_t reg_sspm_ddr_en_0_mask_b; |
| 207 | /* [5] */ |
| 208 | uint8_t reg_scp_srcclkena_mask_b; |
| 209 | /* [6] */ |
| 210 | uint8_t reg_scp_infra_req_mask_b; |
| 211 | /* [7] */ |
| 212 | uint8_t reg_scp_apsrc_req_mask_b; |
| 213 | /* [8] */ |
| 214 | uint8_t reg_scp_vrf18_req_mask_b; |
| 215 | /* [9] */ |
| 216 | uint8_t reg_scp_ddr_en_mask_b; |
| 217 | /* [10] */ |
| 218 | uint8_t reg_audio_dsp_srcclkena_mask_b; |
| 219 | /* [11] */ |
| 220 | uint8_t reg_audio_dsp_infra_req_mask_b; |
| 221 | /* [12] */ |
| 222 | uint8_t reg_audio_dsp_apsrc_req_mask_b; |
| 223 | /* [13] */ |
| 224 | uint8_t reg_audio_dsp_vrf18_req_mask_b; |
| 225 | /* [14] */ |
| 226 | uint8_t reg_audio_dsp_ddr_en_mask_b; |
| 227 | /* [15] */ |
| 228 | uint8_t reg_apu_srcclkena_mask_b; |
| 229 | /* [16] */ |
| 230 | uint8_t reg_apu_infra_req_mask_b; |
| 231 | /* [17] */ |
| 232 | uint8_t reg_apu_apsrc_req_mask_b; |
| 233 | /* [18] */ |
| 234 | uint8_t reg_apu_vrf18_req_mask_b; |
| 235 | /* [19] */ |
| 236 | uint8_t reg_apu_ddr_en_mask_b; |
| 237 | /* [20] */ |
| 238 | uint8_t reg_cpueb_srcclkena_mask_b; |
| 239 | /* [21] */ |
| 240 | uint8_t reg_cpueb_infra_req_mask_b; |
| 241 | /* [22] */ |
| 242 | uint8_t reg_cpueb_apsrc_req_mask_b; |
| 243 | /* [23] */ |
| 244 | uint8_t reg_cpueb_vrf18_req_mask_b; |
| 245 | /* [24] */ |
| 246 | uint8_t reg_cpueb_ddr_en_mask_b; |
| 247 | /* [25] */ |
| 248 | uint8_t reg_bak_psri_srcclkena_mask_b; |
| 249 | /* [26] */ |
| 250 | uint8_t reg_bak_psri_infra_req_mask_b; |
| 251 | /* [27] */ |
| 252 | uint8_t reg_bak_psri_apsrc_req_mask_b; |
| 253 | /* [28] */ |
| 254 | uint8_t reg_bak_psri_vrf18_req_mask_b; |
| 255 | /* [29] */ |
| 256 | uint8_t reg_bak_psri_ddr_en_mask_b; |
| 257 | /* [30] */ |
| 258 | uint8_t reg_cam_ddren_req_mask_b; |
| 259 | /* [31] */ |
| 260 | uint8_t reg_img_ddren_req_mask_b; |
| 261 | |
| 262 | /* SPM_SRC2_MASK */ |
| 263 | /* [0] */ |
| 264 | uint8_t reg_msdc0_srcclkena_mask_b; |
| 265 | /* [1] */ |
| 266 | uint8_t reg_msdc0_infra_req_mask_b; |
| 267 | /* [2] */ |
| 268 | uint8_t reg_msdc0_apsrc_req_mask_b; |
| 269 | /* [3] */ |
| 270 | uint8_t reg_msdc0_vrf18_req_mask_b; |
| 271 | /* [4] */ |
| 272 | uint8_t reg_msdc0_ddr_en_mask_b; |
| 273 | /* [5] */ |
| 274 | uint8_t reg_msdc1_srcclkena_mask_b; |
| 275 | /* [6] */ |
| 276 | uint8_t reg_msdc1_infra_req_mask_b; |
| 277 | /* [7] */ |
| 278 | uint8_t reg_msdc1_apsrc_req_mask_b; |
| 279 | /* [8] */ |
| 280 | uint8_t reg_msdc1_vrf18_req_mask_b; |
| 281 | /* [9] */ |
| 282 | uint8_t reg_msdc1_ddr_en_mask_b; |
| 283 | /* [10] */ |
| 284 | uint8_t reg_msdc2_srcclkena_mask_b; |
| 285 | /* [11] */ |
| 286 | uint8_t reg_msdc2_infra_req_mask_b; |
| 287 | /* [12] */ |
| 288 | uint8_t reg_msdc2_apsrc_req_mask_b; |
| 289 | /* [13] */ |
| 290 | uint8_t reg_msdc2_vrf18_req_mask_b; |
| 291 | /* [14] */ |
| 292 | uint8_t reg_msdc2_ddr_en_mask_b; |
| 293 | /* [15] */ |
| 294 | uint8_t reg_ufs_srcclkena_mask_b; |
| 295 | /* [16] */ |
| 296 | uint8_t reg_ufs_infra_req_mask_b; |
| 297 | /* [17] */ |
| 298 | uint8_t reg_ufs_apsrc_req_mask_b; |
| 299 | /* [18] */ |
| 300 | uint8_t reg_ufs_vrf18_req_mask_b; |
| 301 | /* [19] */ |
| 302 | uint8_t reg_ufs_ddr_en_mask_b; |
| 303 | /* [20] */ |
| 304 | uint8_t reg_usb_srcclkena_mask_b; |
| 305 | /* [21] */ |
| 306 | uint8_t reg_usb_infra_req_mask_b; |
| 307 | /* [22] */ |
| 308 | uint8_t reg_usb_apsrc_req_mask_b; |
| 309 | /* [23] */ |
| 310 | uint8_t reg_usb_vrf18_req_mask_b; |
| 311 | /* [24] */ |
| 312 | uint8_t reg_usb_ddr_en_mask_b; |
| 313 | /* [25] */ |
| 314 | uint8_t reg_pextp_p0_srcclkena_mask_b; |
| 315 | /* [26] */ |
| 316 | uint8_t reg_pextp_p0_infra_req_mask_b; |
| 317 | /* [27] */ |
| 318 | uint8_t reg_pextp_p0_apsrc_req_mask_b; |
| 319 | /* [28] */ |
| 320 | uint8_t reg_pextp_p0_vrf18_req_mask_b; |
| 321 | /* [29] */ |
| 322 | uint8_t reg_pextp_p0_ddr_en_mask_b; |
| 323 | |
| 324 | /* SPM_SRC3_MASK */ |
| 325 | /* [0] */ |
| 326 | uint8_t reg_pextp_p1_srcclkena_mask_b; |
| 327 | /* [1] */ |
| 328 | uint8_t reg_pextp_p1_infra_req_mask_b; |
| 329 | /* [2] */ |
| 330 | uint8_t reg_pextp_p1_apsrc_req_mask_b; |
| 331 | /* [3] */ |
| 332 | uint8_t reg_pextp_p1_vrf18_req_mask_b; |
| 333 | /* [4] */ |
| 334 | uint8_t reg_pextp_p1_ddr_en_mask_b; |
| 335 | /* [5] */ |
| 336 | uint8_t reg_gce0_infra_req_mask_b; |
| 337 | /* [6] */ |
| 338 | uint8_t reg_gce0_apsrc_req_mask_b; |
| 339 | /* [7] */ |
| 340 | uint8_t reg_gce0_vrf18_req_mask_b; |
| 341 | /* [8] */ |
| 342 | uint8_t reg_gce0_ddr_en_mask_b; |
| 343 | /* [9] */ |
| 344 | uint8_t reg_gce1_infra_req_mask_b; |
| 345 | /* [10] */ |
| 346 | uint8_t reg_gce1_apsrc_req_mask_b; |
| 347 | /* [11] */ |
| 348 | uint8_t reg_gce1_vrf18_req_mask_b; |
| 349 | /* [12] */ |
| 350 | uint8_t reg_gce1_ddr_en_mask_b; |
| 351 | /* [13] */ |
| 352 | uint8_t reg_spm_srcclkena_reserved_mask_b; |
| 353 | /* [14] */ |
| 354 | uint8_t reg_spm_infra_req_reserved_mask_b; |
| 355 | /* [15] */ |
| 356 | uint8_t reg_spm_apsrc_req_reserved_mask_b; |
| 357 | /* [16] */ |
| 358 | uint8_t reg_spm_vrf18_req_reserved_mask_b; |
| 359 | /* [17] */ |
| 360 | uint8_t reg_spm_ddr_en_reserved_mask_b; |
| 361 | /* [18] */ |
| 362 | uint8_t reg_disp0_apsrc_req_mask_b; |
| 363 | /* [19] */ |
| 364 | uint8_t reg_disp0_ddr_en_mask_b; |
| 365 | /* [20] */ |
| 366 | uint8_t reg_disp1_apsrc_req_mask_b; |
| 367 | /* [21] */ |
| 368 | uint8_t reg_disp1_ddr_en_mask_b; |
| 369 | /* [22] */ |
| 370 | uint8_t reg_disp2_apsrc_req_mask_b; |
| 371 | /* [23] */ |
| 372 | uint8_t reg_disp2_ddr_en_mask_b; |
| 373 | /* [24] */ |
| 374 | uint8_t reg_disp3_apsrc_req_mask_b; |
| 375 | /* [25] */ |
| 376 | uint8_t reg_disp3_ddr_en_mask_b; |
| 377 | /* [26] */ |
| 378 | uint8_t reg_infrasys_apsrc_req_mask_b; |
| 379 | /* [27] */ |
| 380 | uint8_t reg_infrasys_ddr_en_mask_b; |
| 381 | /* [28] */ |
| 382 | uint8_t reg_cg_check_srcclkena_mask_b; |
| 383 | /* [29] */ |
| 384 | uint8_t reg_cg_check_apsrc_req_mask_b; |
| 385 | /* [30] */ |
| 386 | uint8_t reg_cg_check_vrf18_req_mask_b; |
| 387 | /* [31] */ |
| 388 | uint8_t reg_cg_check_ddr_en_mask_b; |
| 389 | |
| 390 | /* SPM_SRC4_MASK */ |
| 391 | /* [8:0] */ |
| 392 | uint32_t reg_mcusys_merge_apsrc_req_mask_b; |
| 393 | /* [17:9] */ |
| 394 | uint32_t reg_mcusys_merge_ddr_en_mask_b; |
| 395 | /* [19:18] */ |
| 396 | uint8_t reg_dramc_md32_infra_req_mask_b; |
| 397 | /* [21:20] */ |
| 398 | uint8_t reg_dramc_md32_vrf18_req_mask_b; |
| 399 | /* [23:22] */ |
| 400 | uint8_t reg_dramc_md32_ddr_en_mask_b; |
| 401 | /* [24] */ |
| 402 | uint8_t reg_dvfsrc_event_trigger_mask_b; |
| 403 | |
| 404 | /* SPM_WAKEUP_EVENT_MASK2 */ |
| 405 | /* [3:0] */ |
| 406 | uint8_t reg_sc_sw2spm_wakeup_mask_b; |
| 407 | /* [4] */ |
| 408 | uint8_t reg_sc_adsp2spm_wakeup_mask_b; |
| 409 | /* [8:5] */ |
| 410 | uint8_t reg_sc_sspm2spm_wakeup_mask_b; |
| 411 | /* [9] */ |
| 412 | uint8_t reg_sc_scp2spm_wakeup_mask_b; |
| 413 | /* [10] */ |
| 414 | uint8_t reg_csyspwrup_ack_mask; |
| 415 | /* [11] */ |
| 416 | uint8_t reg_csyspwrup_req_mask; |
| 417 | |
| 418 | /* SPM_WAKEUP_EVENT_MASK */ |
| 419 | /* [31:0] */ |
| 420 | uint32_t reg_wakeup_event_mask; |
| 421 | |
| 422 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 423 | /* [31:0] */ |
| 424 | uint32_t reg_ext_wakeup_event_mask; |
| 425 | }; |
| 426 | |
| 427 | /* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */ |
| 428 | enum pwr_ctrl_enum { |
| 429 | PW_PCM_FLAGS, |
| 430 | PW_PCM_FLAGS_CUST, |
| 431 | PW_PCM_FLAGS_CUST_SET, |
| 432 | PW_PCM_FLAGS_CUST_CLR, |
| 433 | PW_PCM_FLAGS1, |
| 434 | PW_PCM_FLAGS1_CUST, |
| 435 | PW_PCM_FLAGS1_CUST_SET, |
| 436 | PW_PCM_FLAGS1_CUST_CLR, |
| 437 | PW_TIMER_VAL, |
| 438 | PW_TIMER_VAL_CUST, |
| 439 | PW_TIMER_VAL_RAMP_EN, |
| 440 | PW_TIMER_VAL_RAMP_EN_SEC, |
| 441 | PW_WAKE_SRC, |
| 442 | PW_WAKE_SRC_CUST, |
| 443 | PW_WDT_DISABLE, |
| 444 | |
| 445 | /* SPM_AP_STANDBY_CON */ |
| 446 | PW_REG_WFI_OP, |
| 447 | PW_REG_WFI_TYPE, |
| 448 | PW_REG_MP0_CPUTOP_IDLE_MASK, |
| 449 | PW_REG_MP1_CPUTOP_IDLE_MASK, |
| 450 | PW_REG_MCUSYS_IDLE_MASK, |
| 451 | PW_REG_MD_APSRC_1_SEL, |
| 452 | PW_REG_MD_APSRC_0_SEL, |
| 453 | PW_REG_CONN_APSRC_SEL, |
| 454 | |
| 455 | /* SPM_SRC_REQ */ |
| 456 | PW_REG_SPM_APSRC_REQ, |
| 457 | PW_REG_SPM_F26M_REQ, |
| 458 | PW_REG_SPM_INFRA_REQ, |
| 459 | PW_REG_SPM_VRF18_REQ, |
| 460 | PW_REG_SPM_DDR_EN_REQ, |
| 461 | PW_REG_SPM_DVFS_REQ, |
| 462 | PW_REG_SPM_SW_MAILBOX_REQ, |
| 463 | PW_REG_SPM_SSPM_MAILBOX_REQ, |
| 464 | PW_REG_SPM_ADSP_MAILBOX_REQ, |
| 465 | PW_REG_SPM_SCP_MAILBOX_REQ, |
| 466 | |
| 467 | /* SPM_SRC_MASK */ |
| 468 | PW_REG_SSPM_SRCCLKENA_0_MASK_B, |
| 469 | PW_REG_SSPM_INFRA_REQ_0_MASK_B, |
| 470 | PW_REG_SSPM_APSRC_REQ_0_MASK_B, |
| 471 | PW_REG_SSPM_VRF18_REQ_0_MASK_B, |
| 472 | PW_REG_SSPM_DDR_EN_0_MASK_B, |
| 473 | PW_REG_SCP_SRCCLKENA_MASK_B, |
| 474 | PW_REG_SCP_INFRA_REQ_MASK_B, |
| 475 | PW_REG_SCP_APSRC_REQ_MASK_B, |
| 476 | PW_REG_SCP_VRF18_REQ_MASK_B, |
| 477 | PW_REG_SCP_DDR_EN_MASK_B, |
| 478 | PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B, |
| 479 | PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B, |
| 480 | PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B, |
| 481 | PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B, |
| 482 | PW_REG_AUDIO_DSP_DDR_EN_MASK_B, |
| 483 | PW_REG_APU_SRCCLKENA_MASK_B, |
| 484 | PW_REG_APU_INFRA_REQ_MASK_B, |
| 485 | PW_REG_APU_APSRC_REQ_MASK_B, |
| 486 | PW_REG_APU_VRF18_REQ_MASK_B, |
| 487 | PW_REG_APU_DDR_EN_MASK_B, |
| 488 | PW_REG_CPUEB_SRCCLKENA_MASK_B, |
| 489 | PW_REG_CPUEB_INFRA_REQ_MASK_B, |
| 490 | PW_REG_CPUEB_APSRC_REQ_MASK_B, |
| 491 | PW_REG_CPUEB_VRF18_REQ_MASK_B, |
| 492 | PW_REG_CPUEB_DDR_EN_MASK_B, |
| 493 | PW_REG_BAK_PSRI_SRCCLKENA_MASK_B, |
| 494 | PW_REG_BAK_PSRI_INFRA_REQ_MASK_B, |
| 495 | PW_REG_BAK_PSRI_APSRC_REQ_MASK_B, |
| 496 | PW_REG_BAK_PSRI_VRF18_REQ_MASK_B, |
| 497 | PW_REG_BAK_PSRI_DDR_EN_MASK_B, |
| 498 | PW_REG_CAM_DDREN_REQ_MASK_B, |
| 499 | PW_REG_IMG_DDREN_REQ_MASK_B, |
| 500 | |
| 501 | /* SPM_SRC2_MASK */ |
| 502 | PW_REG_MSDC0_SRCCLKENA_MASK_B, |
| 503 | PW_REG_MSDC0_INFRA_REQ_MASK_B, |
| 504 | PW_REG_MSDC0_APSRC_REQ_MASK_B, |
| 505 | PW_REG_MSDC0_VRF18_REQ_MASK_B, |
| 506 | PW_REG_MSDC0_DDR_EN_MASK_B, |
| 507 | PW_REG_MSDC1_SRCCLKENA_MASK_B, |
| 508 | PW_REG_MSDC1_INFRA_REQ_MASK_B, |
| 509 | PW_REG_MSDC1_APSRC_REQ_MASK_B, |
| 510 | PW_REG_MSDC1_VRF18_REQ_MASK_B, |
| 511 | PW_REG_MSDC1_DDR_EN_MASK_B, |
| 512 | PW_REG_MSDC2_SRCCLKENA_MASK_B, |
| 513 | PW_REG_MSDC2_INFRA_REQ_MASK_B, |
| 514 | PW_REG_MSDC2_APSRC_REQ_MASK_B, |
| 515 | PW_REG_MSDC2_VRF18_REQ_MASK_B, |
| 516 | PW_REG_MSDC2_DDR_EN_MASK_B, |
| 517 | PW_REG_UFS_SRCCLKENA_MASK_B, |
| 518 | PW_REG_UFS_INFRA_REQ_MASK_B, |
| 519 | PW_REG_UFS_APSRC_REQ_MASK_B, |
| 520 | PW_REG_UFS_VRF18_REQ_MASK_B, |
| 521 | PW_REG_UFS_DDR_EN_MASK_B, |
| 522 | PW_REG_USB_SRCCLKENA_MASK_B, |
| 523 | PW_REG_USB_INFRA_REQ_MASK_B, |
| 524 | PW_REG_USB_APSRC_REQ_MASK_B, |
| 525 | PW_REG_USB_VRF18_REQ_MASK_B, |
| 526 | PW_REG_USB_DDR_EN_MASK_B, |
| 527 | PW_REG_PEXTP_P0_SRCCLKENA_MASK_B, |
| 528 | PW_REG_PEXTP_P0_INFRA_REQ_MASK_B, |
| 529 | PW_REG_PEXTP_P0_APSRC_REQ_MASK_B, |
| 530 | PW_REG_PEXTP_P0_VRF18_REQ_MASK_B, |
| 531 | PW_REG_PEXTP_P0_DDR_EN_MASK_B, |
| 532 | |
| 533 | /* SPM_SRC3_MASK */ |
| 534 | PW_REG_PEXTP_P1_SRCCLKENA_MASK_B, |
| 535 | PW_REG_PEXTP_P1_INFRA_REQ_MASK_B, |
| 536 | PW_REG_PEXTP_P1_APSRC_REQ_MASK_B, |
| 537 | PW_REG_PEXTP_P1_VRF18_REQ_MASK_B, |
| 538 | PW_REG_PEXTP_P1_DDR_EN_MASK_B, |
| 539 | PW_REG_GCE0_INFRA_REQ_MASK_B, |
| 540 | PW_REG_GCE0_APSRC_REQ_MASK_B, |
| 541 | PW_REG_GCE0_VRF18_REQ_MASK_B, |
| 542 | PW_REG_GCE0_DDR_EN_MASK_B, |
| 543 | PW_REG_GCE1_INFRA_REQ_MASK_B, |
| 544 | PW_REG_GCE1_APSRC_REQ_MASK_B, |
| 545 | PW_REG_GCE1_VRF18_REQ_MASK_B, |
| 546 | PW_REG_GCE1_DDR_EN_MASK_B, |
| 547 | PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B, |
| 548 | PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B, |
| 549 | PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B, |
| 550 | PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B, |
| 551 | PW_REG_SPM_DDR_EN_RESERVED_MASK_B, |
| 552 | PW_REG_DISP0_APSRC_REQ_MASK_B, |
| 553 | PW_REG_DISP0_DDR_EN_MASK_B, |
| 554 | PW_REG_DISP1_APSRC_REQ_MASK_B, |
| 555 | PW_REG_DISP1_DDR_EN_MASK_B, |
| 556 | PW_REG_DISP2_APSRC_REQ_MASK_B, |
| 557 | PW_REG_DISP2_DDR_EN_MASK_B, |
| 558 | PW_REG_DISP3_APSRC_REQ_MASK_B, |
| 559 | PW_REG_DISP3_DDR_EN_MASK_B, |
| 560 | PW_REG_INFRASYS_APSRC_REQ_MASK_B, |
| 561 | PW_REG_INFRASYS_DDR_EN_MASK_B, |
| 562 | PW_REG_CG_CHECK_SRCCLKENA_MASK_B, |
| 563 | PW_REG_CG_CHECK_APSRC_REQ_MASK_B, |
| 564 | PW_REG_CG_CHECK_VRF18_REQ_MASK_B, |
| 565 | PW_REG_CG_CHECK_DDR_EN_MASK_B, |
| 566 | |
| 567 | /* SPM_SRC4_MASK */ |
| 568 | PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B, |
| 569 | PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B, |
| 570 | PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B, |
| 571 | PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B, |
| 572 | PW_REG_DRAMC_MD32_DDR_EN_MASK_B, |
| 573 | PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B, |
| 574 | |
| 575 | /* SPM_WAKEUP_EVENT_MASK2 */ |
| 576 | PW_REG_SC_SW2SPM_WAKEUP_MASK_B, |
| 577 | PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B, |
| 578 | PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B, |
| 579 | PW_REG_SC_SCP2SPM_WAKEUP_MASK_B, |
| 580 | PW_REG_CSYSPWRUP_ACK_MASK, |
| 581 | PW_REG_CSYSPWRUP_REQ_MASK, |
| 582 | |
| 583 | /* SPM_WAKEUP_EVENT_MASK */ |
| 584 | PW_REG_WAKEUP_EVENT_MASK, |
| 585 | |
| 586 | /* SPM_WAKEUP_EVENT_EXT_MASK */ |
| 587 | PW_REG_EXT_WAKEUP_EVENT_MASK, |
| 588 | PW_MAX_COUNT, |
| 589 | }; |
| 590 | |
| 591 | /* spm_internal.c internal status */ |
| 592 | #define SPM_INTERNAL_STATUS_HW_S1 BIT(0) |
| 593 | #define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800) |
| 594 | /* BIT[0]: SW_EN, BIT[4]: STA_EN, BIT[8]: HW_EN */ |
| 595 | #define SPM_ACK_CHK_3_CON_EN (0x110) |
| 596 | #define SPM_ACK_CHK_3_CON_CLR_ALL (0x2) |
| 597 | /* BIT[15]: RESULT */ |
| 598 | #define SPM_ACK_CHK_3_CON_RESULT (0x8000) |
| 599 | |
| 600 | struct wake_status_trace_comm { |
| 601 | uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */ |
| 602 | uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */ |
| 603 | uint32_t timer_out; /* SPM_SW_RSV_6*/ |
| 604 | uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */ |
| 605 | uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */ |
| 606 | uint32_t r12; /* SPM_SW_RSV_0 */ |
| 607 | uint32_t r13; /* PCM_REG13_DATA */ |
| 608 | uint32_t req_sta0; /* SRC_REQ_STA_0 */ |
| 609 | uint32_t req_sta1; /* SRC_REQ_STA_1 */ |
| 610 | uint32_t req_sta2; /* SRC_REQ_STA_2 */ |
| 611 | uint32_t req_sta3; /* SRC_REQ_STA_3 */ |
| 612 | uint32_t req_sta4; /* SRC_REQ_STA_4 */ |
| 613 | uint32_t raw_sta; /* SPM_WAKEUP_STA */ |
| 614 | uint32_t times_h; /* timestamp high bits */ |
| 615 | uint32_t times_l; /* timestamp low bits */ |
| 616 | uint32_t resumetime; /* timestamp low bits */ |
| 617 | }; |
| 618 | |
| 619 | struct wake_status_trace { |
| 620 | struct wake_status_trace_comm comm; |
| 621 | }; |
| 622 | |
| 623 | struct wake_status { |
| 624 | struct wake_status_trace tr; |
| 625 | uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */ |
| 626 | uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */ |
| 627 | uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */ |
| 628 | uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */ |
| 629 | uint32_t wake_misc; /* SPM_SW_RSV_5 */ |
| 630 | uint32_t idle_sta; /* SUBSYS_IDLE_STA */ |
developer | 68ff2df | 2023-05-03 19:11:29 +0800 | [diff] [blame] | 631 | uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */ |
developer | 6514957 | 2022-09-07 18:26:57 +0800 | [diff] [blame] | 632 | uint32_t sw_flag0; /* SPM_SW_FLAG_0 */ |
| 633 | uint32_t sw_flag1; /* SPM_SW_FLAG_1 */ |
| 634 | uint32_t isr; /* SPM_IRQ_STA */ |
developer | 68ff2df | 2023-05-03 19:11:29 +0800 | [diff] [blame] | 635 | uint32_t clk_settle; /* SPM_CLK_SETTLE */ |
| 636 | uint32_t src_req; /* SPM_SRC_REQ */ |
developer | 6514957 | 2022-09-07 18:26:57 +0800 | [diff] [blame] | 637 | uint32_t log_index; |
| 638 | uint32_t is_abort; |
developer | 68ff2df | 2023-05-03 19:11:29 +0800 | [diff] [blame] | 639 | uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */ |
| 640 | uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */ |
| 641 | uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */ |
| 642 | uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */ |
| 643 | uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */ |
developer | 6514957 | 2022-09-07 18:26:57 +0800 | [diff] [blame] | 644 | }; |
| 645 | |
| 646 | struct spm_lp_scen { |
| 647 | struct pcm_desc *pcmdesc; |
| 648 | struct pwr_ctrl *pwrctrl; |
| 649 | }; |
| 650 | |
| 651 | void __spm_set_cpu_status(unsigned int cpu); |
| 652 | void __spm_src_req_update(const struct pwr_ctrl *pwrctrl, unsigned int resource_usage); |
| 653 | void __spm_set_power_control(const struct pwr_ctrl *pwrctrl); |
| 654 | void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); |
| 655 | void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl); |
| 656 | void __spm_send_cpu_wakeup_event(void); |
| 657 | void __spm_get_wakeup_status(struct wake_status *wakesta, unsigned int ext_status); |
| 658 | void __spm_clean_after_wakeup(void); |
| 659 | wake_reason_t __spm_output_wake_reason(const struct wake_status *wakesta); |
| 660 | void __spm_set_pcm_wdt(int en); |
| 661 | void __spm_ext_int_wakeup_req_clr(void); |
| 662 | void __spm_hw_s1_state_monitor(int en, unsigned int *status); |
| 663 | |
| 664 | static inline void spm_hw_s1_state_monitor_resume(void) |
| 665 | { |
| 666 | __spm_hw_s1_state_monitor(1, NULL); |
| 667 | } |
| 668 | |
| 669 | static inline void spm_hw_s1_state_monitor_pause(unsigned int *status) |
| 670 | { |
| 671 | __spm_hw_s1_state_monitor(0, status); |
| 672 | } |
| 673 | |
| 674 | void __spm_clean_before_wfi(void); |
| 675 | |
| 676 | #endif /* MT_SPM_INTERNAL */ |