Konstantin Porotchkin | af3d529 | 2018-02-26 16:32:35 +0200 | [diff] [blame] | 1 | TF-A Porting Guide |
| 2 | ================= |
| 3 | |
| 4 | This section describes how to port TF-A to a customer board, assuming that the SoC being used is already supported |
| 5 | in TF-A. |
| 6 | |
| 7 | |
| 8 | Source Code Structure |
| 9 | --------------------- |
| 10 | - The customer platform specific code shall reside under "plat/marvell/<soc family>/<soc>_cust" |
| 11 | (e.g. 'plat/marvell/a8k/a7040_cust'). |
| 12 | - The platform name for build purposes is called "<soc>_cust" (e.g. a7040_cust). |
| 13 | - The build system will reuse all files from within the soc directory, and take only the porting |
| 14 | files from the customer platform directory. |
| 15 | |
| 16 | Files that require porting are located at "plat/marvell/<soc family>/<soc>_cust" directory. |
| 17 | |
| 18 | |
| 19 | Armada-70x0/Armada-80x0 Porting |
| 20 | ------------------------------- |
| 21 | |
| 22 | - SoC Physical Address Map (marvell_plat_config.c): |
| 23 | - This file describes the SoC physical memory mapping to be used for the CCU, IOWIN, AXI-MBUS and IOB |
| 24 | address decode units (Refer to the functional spec for more details). |
| 25 | - In most cases, using the default address decode windows should work OK. |
| 26 | - In cases where a special physical address map is needed (e.g. Special size for PCIe MEM windows, |
| 27 | large memory mapped SPI flash...), then porting of the SoC memory map is required. |
| 28 | - Note: For a detailed information on how CCU, IOWIN, AXI-MBUS & IOB work, please refer to the SoC functional spec, |
| 29 | and under "docs/marvell/misc/mvebu-[ccu/iob/amb/io-win].txt" files. |
| 30 | |
| 31 | - boot loader recovery (marvell_plat_config.c): |
| 32 | - Background: |
| 33 | boot rom can skip the current image and choose to boot from next position if a specific value |
| 34 | (0xDEADB002) is returned by the ble main function. This feature is used for boot loader recovery |
| 35 | by booting from a valid flash-image saved in next position on flash (e.g. address 2M in SPI flash). |
| 36 | |
| 37 | Supported options to implement the skip request are: |
| 38 | - GPIO |
| 39 | - I2C |
| 40 | - User defined |
| 41 | |
| 42 | - Porting: |
| 43 | Under marvell_plat_config.c, implement struct skip_image that includes specific board parameters. |
| 44 | .. warning:: to disable this feature make sure the struct skip_image is not implemented. |
| 45 | |
| 46 | - Example: |
| 47 | In A7040-DB specific implementation (plat/marvell/a8k/a70x0/board/marvell_plat_config.c), |
| 48 | the image skip is implemented using GPIO: mpp 33 (SW5). |
| 49 | |
| 50 | Before resetting the board make sure there is a valid image on the next flash address: |
| 51 | -tftp [valid address] flash-image.bin |
| 52 | -sf update [valid address] 0x2000000 [size] |
| 53 | |
| 54 | Press reset and keep pressing the button connected to the chosen GPIO pin. A skip image request |
| 55 | message is printed on the screen and boot rom boots from the saved image at the next position. |
| 56 | |
| 57 | - DDR Porting (dram_port.c): |
| 58 | - This file defines the dram topology and parameters of the target board. |
| 59 | - The DDR code is part of the BLE component, which is an extension of ARM Trusted Firmware (TF-A). |
| 60 | - The DDR driver called mv_ddr is released separately apart from TF-A sources. |
| 61 | - The BLE and consequently, the DDR init code is executed at the early stage of the boot process. |
| 62 | - Each supported platform of the TF-A has its own DDR porting file called dram_port.c located at |
| 63 | ``atf/plat/marvell/a8k/<platform>/board`` directory. |
| 64 | - Please refer to '<path_to_mv_ddr_sources>/doc/porting_guide.txt' for detailed porting description. |
| 65 | - The build target directory is "build/<platform>/release/ble". |
| 66 | |