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Varun Wadekarb316e242015-05-19 16:48:04 +05301#
Varun Wadekar396530b2019-03-01 10:18:35 -08002# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar8760ec92018-06-13 14:54:01 -07003# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +05304#
dp-armfa3cf0b2017-05-03 09:38:09 +01005# SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +05306#
7
Varun Wadekara78bb1b2015-08-07 10:03:00 +05308SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC}
9
Varun Wadekara441f722017-04-26 13:46:11 -070010# dump the state on crash console
11CRASH_REPORTING := 1
12$(eval $(call add_define,CRASH_REPORTING))
Varun Wadekar6077dce2016-01-27 11:31:06 -080013
Varun Wadekar38c80222017-04-26 13:48:19 -070014# enable assert() for release/debug builds
15ENABLE_ASSERTIONS := 1
Varun Wadekar96658a92017-08-03 11:38:32 -070016PLAT_LOG_LEVEL_ASSERT := 40
17$(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT))
Varun Wadekar38c80222017-04-26 13:48:19 -070018
Varun Wadekara441f722017-04-26 13:46:11 -070019# enable dynamic memory mapping
20PLAT_XLAT_TABLES_DYNAMIC := 1
21$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
22
23# Enable PSCI v1.0 extended state ID format
24PSCI_EXTENDED_STATE_ID := 1
25
26# code and read-only data should be put on separate memory pages
27SEPARATE_CODE_AND_RODATA := 1
28
29# do not use coherent memory
30USE_COHERENT_MEM := 0
31
David Cunadoc5b0c0f2017-10-31 23:19:21 +000032# do not enable SVE
33ENABLE_SVE_FOR_NS := 0
34
Varun Wadekare0ecdd02017-08-03 17:17:00 -070035# enable D-cache early during CPU warmboot
36WARMBOOT_ENABLE_DCACHE_EARLY := 1
37
Anthony Zhouc87bc0c2018-04-02 19:34:59 +080038# remove the standard libc
39OVERRIDE_LIBC := 1
40
Varun Wadekar8760ec92018-06-13 14:54:01 -070041# Flag to enable WDT FIQ interrupt handling for Tegra SoCs
42# prior to Tegra186
43ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0
44
Varun Wadekar0ed62702018-06-20 14:30:59 -070045# Flag to allow relocation of BL32 image to TZDRAM during boot
46RELOCATE_BL32_IMAGE ?= 0
47
Varun Wadekarb316e242015-05-19 16:48:04 +053048include plat/nvidia/tegra/common/tegra_common.mk
49include ${SOC_DIR}/platform_${TARGET_SOC}.mk
Varun Wadekarc39b0ba2015-07-21 10:16:13 +053050
Varun Wadekar8760ec92018-06-13 14:54:01 -070051$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
Varun Wadekar0ed62702018-06-20 14:30:59 -070052$(eval $(call add_define,RELOCATE_BL32_IMAGE))
Varun Wadekar8760ec92018-06-13 14:54:01 -070053
Varun Wadekarc39b0ba2015-07-21 10:16:13 +053054# modify BUILD_PLAT to point to SoC specific build directory
55BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
Varun Wadekar66231d12017-06-07 09:57:42 -070056
Varun Wadekar7919a602017-09-06 17:17:12 -070057# platform cflags (enable signed comparisons, disable stdlib)
58TF_CFLAGS += -Wsign-compare -nostdlib
Anthony Zhouc87bc0c2018-04-02 19:34:59 +080059
60# override with necessary libc files for the Tegra platform
61override LIBC_SRCS := $(addprefix lib/libc/, \
62 assert.c \
63 memcpy.c \
64 memmove.c \
65 memset.c \
66 printf.c \
67 putchar.c \
68 strlen.c \
69 snprintf.c)
70
71INCLUDES += -Iinclude/lib/libc \
72 -Iinclude/lib/libc/$(ARCH) \
Varun Wadekar4d034c52019-01-11 14:47:48 -080073
74ifneq ($(findstring armlink,$(notdir $(LD))),)
75# o suppress warnings for section mismatches, undefined symbols
76# o use only those libraries that are specified in the input file
77# list to resolve references
78# o create a static callgraph of functions
79# o resolve undefined symbols to el3_panic
80# o include only required sections
81TF_LDFLAGS += --diag_suppress=L6314,L6332 --no_scanlib --callgraph
Varun Wadekar4d034c52019-01-11 14:47:48 -080082TF_LDFLAGS += --keep="*(__pubsub*)" --keep="*(rt_svc_descs*)" --keep="*(*cpu_ops)"
83ifeq (${ENABLE_PMF},1)
84TF_LDFLAGS += --keep="*(*pmf_svc_descs*)"
85endif
86endif