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Antonio Nino Diazc326c342019-01-11 11:20:10 +00001/*
Andre Przywarabb0db3b2023-01-25 12:26:14 +00002 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Antonio Nino Diazc326c342019-01-11 11:20:10 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef ARCH_FEATURES_H
8#define ARCH_FEATURES_H
9
10#include <stdbool.h>
11
12#include <arch_helpers.h>
Andre Przywarae8920f62022-11-10 14:28:01 +000013#include <common/feat_detect.h>
Antonio Nino Diazc326c342019-01-11 11:20:10 +000014
Andre Przywarabb0db3b2023-01-25 12:26:14 +000015#define ISOLATE_FIELD(reg, feat) \
Andre Przywara0dda4242023-04-18 16:58:36 +010016 ((unsigned int)(((reg) >> (feat)) & ID_REG_FIELD_MASK))
Andre Przywarabb0db3b2023-01-25 12:26:14 +000017
Andre Przywara0dda4242023-04-18 16:58:36 +010018#define CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard) \
19static inline bool is_ ## name ## _supported(void) \
20{ \
21 if ((guard) == FEAT_STATE_DISABLED) { \
22 return false; \
23 } \
24 if ((guard) == FEAT_STATE_ALWAYS) { \
25 return true; \
26 } \
27 return read_func() >= (idvalue); \
Antonio Nino Diazd29d21e2019-02-06 09:23:04 +000028}
29
Andre Przywara0dda4242023-04-18 16:58:36 +010030#define CREATE_FEATURE_FUNCS(name, idreg, idfield, guard) \
31static unsigned int read_ ## name ## _id_field(void) \
32{ \
33 return ISOLATE_FIELD(read_ ## idreg(), idfield); \
34} \
35CREATE_FEATURE_FUNCS_VER(name, read_ ## name ## _id_field, 1U, guard)
Andre Przywara97272942023-01-26 15:27:38 +000036
Andre Przywara0dda4242023-04-18 16:58:36 +010037static inline bool is_armv7_gentimer_present(void)
Andre Przywara98908b32022-11-17 16:42:09 +000038{
Andre Przywara0dda4242023-04-18 16:58:36 +010039 /* The Generic Timer is always present in an ARMv8-A implementation */
40 return true;
Andre Przywara98908b32022-11-17 16:42:09 +000041}
42
Andre Przywara0dda4242023-04-18 16:58:36 +010043CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_PAN_SHIFT,
44 ENABLE_FEAT_PAN)
45CREATE_FEATURE_FUNCS(feat_vhe, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_VHE_SHIFT,
46 ENABLE_FEAT_VHE)
Daniel Boulby44b43332020-11-25 16:36:46 +000047
Antonio Nino Diazc326c342019-01-11 11:20:10 +000048static inline bool is_armv8_2_ttcnp_present(void)
49{
50 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
51 ID_AA64MMFR2_EL1_CNP_MASK) != 0U;
52}
53
Juan Pablo Condee089a172022-06-29 17:44:43 -040054static inline bool is_feat_pacqarma3_present(void)
55{
56 uint64_t mask_id_aa64isar2 =
57 (ID_AA64ISAR2_GPA3_MASK << ID_AA64ISAR2_GPA3_SHIFT) |
58 (ID_AA64ISAR2_APA3_MASK << ID_AA64ISAR2_APA3_SHIFT);
59
60 /* If any of the fields is not zero, QARMA3 algorithm is present */
61 return (read_id_aa64isar2_el1() & mask_id_aa64isar2) != 0U;
62}
63
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000064static inline bool is_armv8_3_pauth_present(void)
65{
Juan Pablo Condee089a172022-06-29 17:44:43 -040066 uint64_t mask_id_aa64isar1 =
67 (ID_AA64ISAR1_GPI_MASK << ID_AA64ISAR1_GPI_SHIFT) |
68 (ID_AA64ISAR1_GPA_MASK << ID_AA64ISAR1_GPA_SHIFT) |
69 (ID_AA64ISAR1_API_MASK << ID_AA64ISAR1_API_SHIFT) |
70 (ID_AA64ISAR1_APA_MASK << ID_AA64ISAR1_APA_SHIFT);
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000071
Juan Pablo Condee089a172022-06-29 17:44:43 -040072 /*
73 * If any of the fields is not zero or QARMA3 is present,
74 * PAuth is present
75 */
76 return ((read_id_aa64isar1_el1() & mask_id_aa64isar1) != 0U ||
77 is_feat_pacqarma3_present());
Antonio Nino Diaz25cda672019-02-19 11:53:51 +000078}
79
Sathees Balya74155972019-01-25 11:36:01 +000080static inline bool is_armv8_4_ttst_present(void)
81{
82 return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
83 ID_AA64MMFR2_EL1_ST_MASK) == 1U;
84}
85
Alexei Fedorov90f2e882019-05-24 12:17:09 +010086static inline bool is_armv8_5_bti_present(void)
87{
88 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_BT_SHIFT) &
89 ID_AA64PFR1_EL1_BT_MASK) == BTI_IMPLEMENTED;
90}
91
Soby Mathew830f0ad2019-07-12 09:23:38 +010092static inline unsigned int get_armv8_5_mte_support(void)
93{
94 return ((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) &
95 ID_AA64PFR1_EL1_MTE_MASK);
96}
97
Andre Przywara0dda4242023-04-18 16:58:36 +010098CREATE_FEATURE_FUNCS(feat_sel2, id_aa64pfr0_el1, ID_AA64PFR0_SEL2_SHIFT,
99 ENABLE_FEAT_SEL2)
100CREATE_FEATURE_FUNCS(feat_twed, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_TWED_SHIFT,
101 ENABLE_FEAT_TWED)
102CREATE_FEATURE_FUNCS(feat_fgt, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_FGT_SHIFT,
103 ENABLE_FEAT_FGT)
104CREATE_FEATURE_FUNCS(feat_mte_perm, id_aa64pfr2_el1,
105 ID_AA64PFR2_EL1_MTEPERM_SHIFT, ENABLE_FEAT_MTE_PERM)
106CREATE_FEATURE_FUNCS(feat_ecv, id_aa64mmfr0_el1, ID_AA64MMFR0_EL1_ECV_SHIFT,
107 ENABLE_FEAT_ECV)
108CREATE_FEATURE_FUNCS_VER(feat_ecv_v2, read_feat_ecv_id_field,
109 ID_AA64MMFR0_EL1_ECV_SELF_SYNCH, ENABLE_FEAT_ECV)
Mark Brownc37eee72023-03-14 20:13:03 +0000110
Andre Przywara0dda4242023-04-18 16:58:36 +0100111CREATE_FEATURE_FUNCS(feat_rng, id_aa64isar0_el1, ID_AA64ISAR0_RNDR_SHIFT,
112 ENABLE_FEAT_RNG)
113CREATE_FEATURE_FUNCS(feat_tcr2, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_TCRX_SHIFT,
114 ENABLE_FEAT_TCR2)
Mark Brown293a6612023-03-14 20:48:43 +0000115
Andre Przywara0dda4242023-04-18 16:58:36 +0100116CREATE_FEATURE_FUNCS(feat_s2poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2POE_SHIFT,
117 ENABLE_FEAT_S2POE)
118CREATE_FEATURE_FUNCS(feat_s1poe, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1POE_SHIFT,
119 ENABLE_FEAT_S1POE)
Mark Brown293a6612023-03-14 20:48:43 +0000120static inline bool is_feat_sxpoe_supported(void)
121{
122 return is_feat_s1poe_supported() || is_feat_s2poe_supported();
123}
124
Andre Przywara0dda4242023-04-18 16:58:36 +0100125CREATE_FEATURE_FUNCS(feat_s2pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S2PIE_SHIFT,
126 ENABLE_FEAT_S2PIE)
127CREATE_FEATURE_FUNCS(feat_s1pie, id_aa64mmfr3_el1, ID_AA64MMFR3_EL1_S1PIE_SHIFT,
128 ENABLE_FEAT_S1PIE)
Mark Brown293a6612023-03-14 20:48:43 +0000129static inline bool is_feat_sxpie_supported(void)
130{
131 return is_feat_s1pie_supported() || is_feat_s2pie_supported();
132}
133
Andre Przywara0dda4242023-04-18 16:58:36 +0100134/* FEAT_GCS: Guarded Control Stack */
135CREATE_FEATURE_FUNCS(feat_gcs, id_aa64pfr1_el1, ID_AA64PFR1_EL1_GCS_SHIFT,
136 ENABLE_FEAT_GCS)
Andre Przywara2c550e32022-11-10 14:41:07 +0000137
Andre Przywara0dda4242023-04-18 16:58:36 +0100138/* FEAT_AMU: Activity Monitors Extension */
139CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
140 ENABLE_FEAT_AMU)
141CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
142 ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)
johpow01fa59c6f2020-10-02 13:41:11 -0500143
Alexei Fedorov19933552020-05-26 13:16:41 +0100144/*
145 * Return MPAM version:
146 *
147 * 0x00: None Armv8.0 or later
148 * 0x01: v0.1 Armv8.4 or later
149 * 0x10: v1.0 Armv8.2 or later
150 * 0x11: v1.1 Armv8.4 or later
151 *
152 */
Andre Przywara84b86532022-11-17 16:42:09 +0000153static inline unsigned int read_feat_mpam_version(void)
Alexei Fedorov19933552020-05-26 13:16:41 +0100154{
155 return (unsigned int)((((read_id_aa64pfr0_el1() >>
156 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
157 ((read_id_aa64pfr1_el1() >>
158 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
159}
160
Andre Przywara0dda4242023-04-18 16:58:36 +0100161CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
162 ENABLE_MPAM_FOR_LOWER_ELS)
Andre Przywaraf20ad902022-11-15 11:45:19 +0000163
Andre Przywara0dda4242023-04-18 16:58:36 +0100164/* FEAT_HCX: Extended Hypervisor Configuration Register */
165CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
166 ENABLE_FEAT_HCX)
johpow01f91e59f2021-08-04 19:38:18 -0500167
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400168static inline bool is_feat_rng_trap_present(void)
169{
170 return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT) &
171 ID_AA64PFR1_EL1_RNDR_TRAP_MASK)
172 == ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED);
173}
174
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500175static inline unsigned int get_armv9_2_feat_rme_support(void)
176{
177 /*
178 * Return the RME version, zero if not supported. This function can be
179 * used as both an integer value for the RME version or compared to zero
180 * to detect RME presence.
181 */
182 return (unsigned int)(read_id_aa64pfr0_el1() >>
183 ID_AA64PFR0_FEAT_RME_SHIFT) & ID_AA64PFR0_FEAT_RME_MASK;
184}
185
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000186/*********************************************************************************
187 * Function to identify the presence of FEAT_SB (Speculation Barrier Instruction)
188 ********************************************************************************/
Andre Przywara46880dc2022-11-17 16:42:09 +0000189static inline unsigned int read_feat_sb_id_field(void)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000190{
Andre Przywara0dda4242023-04-18 16:58:36 +0100191 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT);
Andre Przywara06ea44e2022-11-17 17:30:43 +0000192}
193
Andre Przywara0dda4242023-04-18 16:58:36 +0100194/* FEAT_CSV2_2: Cache Speculation Variant 2 */
195CREATE_FEATURE_FUNCS(feat_csv2, id_aa64pfr0_el1, ID_AA64PFR0_CSV2_SHIFT, 0)
196CREATE_FEATURE_FUNCS_VER(feat_csv2_2, read_feat_csv2_id_field,
197 ID_AA64PFR0_CSV2_2_SUPPORTED, ENABLE_FEAT_CSV2_2)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000198
Andre Przywara0dda4242023-04-18 16:58:36 +0100199/* FEAT_SPE: Statistical Profiling Extension */
200CREATE_FEATURE_FUNCS(feat_spe, id_aa64dfr0_el1, ID_AA64DFR0_PMS_SHIFT,
201 ENABLE_SPE_FOR_NS)
Andre Przywara06ea44e2022-11-17 17:30:43 +0000202
Andre Przywara0dda4242023-04-18 16:58:36 +0100203/* FEAT_SVE: Scalable Vector Extension */
204CREATE_FEATURE_FUNCS(feat_sve, id_aa64pfr0_el1, ID_AA64PFR0_SVE_SHIFT,
205 ENABLE_SVE_FOR_NS)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000206
Andre Przywara0dda4242023-04-18 16:58:36 +0100207/* FEAT_RAS: Reliability, Accessibility, Serviceability */
208CREATE_FEATURE_FUNCS(feat_ras, id_aa64pfr0_el1,
209 ID_AA64PFR0_RAS_SHIFT, ENABLE_FEAT_RAS)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000210
Andre Przywara0dda4242023-04-18 16:58:36 +0100211/* FEAT_DIT: Data Independent Timing instructions */
212CREATE_FEATURE_FUNCS(feat_dit, id_aa64pfr0_el1,
213 ID_AA64PFR0_DIT_SHIFT, ENABLE_FEAT_DIT)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000214
Andre Przywara0dda4242023-04-18 16:58:36 +0100215CREATE_FEATURE_FUNCS(feat_sys_reg_trace, id_aa64dfr0_el1,
216 ID_AA64DFR0_TRACEVER_SHIFT, ENABLE_SYS_REG_TRACE_FOR_NS)
Andre Przywaraedc449d2023-01-27 14:09:20 +0000217
Andre Przywara0dda4242023-04-18 16:58:36 +0100218/* FEAT_TRF: TraceFilter */
219CREATE_FEATURE_FUNCS(feat_trf, id_aa64dfr0_el1, ID_AA64DFR0_TRACEFILT_SHIFT,
220 ENABLE_TRF_FOR_NS)
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000221
Andre Przywara0dda4242023-04-18 16:58:36 +0100222/* FEAT_NV2: Enhanced Nested Virtualization */
223CREATE_FEATURE_FUNCS(feat_nv, id_aa64mmfr2_el1, ID_AA64MMFR2_EL1_NV_SHIFT, 0)
224CREATE_FEATURE_FUNCS_VER(feat_nv2, read_feat_nv_id_field,
225 ID_AA64MMFR2_EL1_NV2_SUPPORTED, CTX_INCLUDE_NEVE_REGS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000226
Andre Przywara0dda4242023-04-18 16:58:36 +0100227/* FEAT_BRBE: Branch Record Buffer Extension */
228CREATE_FEATURE_FUNCS(feat_brbe, id_aa64dfr0_el1, ID_AA64DFR0_BRBE_SHIFT,
229 ENABLE_BRBE_FOR_NS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000230
Andre Przywara0dda4242023-04-18 16:58:36 +0100231/* FEAT_TRBE: Trace Buffer Extension */
232CREATE_FEATURE_FUNCS(feat_trbe, id_aa64dfr0_el1, ID_AA64DFR0_TRACEBUFFER_SHIFT,
233 ENABLE_TRBE_FOR_NS)
Andre Przywarac97c5512022-11-17 16:42:09 +0000234
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000235static inline unsigned int read_feat_sme_fa64_id_field(void)
236{
Andre Przywara0dda4242023-04-18 16:58:36 +0100237 return ISOLATE_FIELD(read_id_aa64smfr0_el1(),
238 ID_AA64SMFR0_EL1_SME_FA64_SHIFT);
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +0000239}
Andre Przywara0dda4242023-04-18 16:58:36 +0100240/* FEAT_SMEx: Scalar Matrix Extension */
241CREATE_FEATURE_FUNCS(feat_sme, id_aa64pfr1_el1, ID_AA64PFR1_EL1_SME_SHIFT,
242 ENABLE_SME_FOR_NS)
243CREATE_FEATURE_FUNCS_VER(feat_sme2, read_feat_sme_id_field,
244 ID_AA64PFR1_EL1_SME2_SUPPORTED, ENABLE_SME2_FOR_NS)
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +0000245
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100246/*******************************************************************************
247 * Function to get hardware granularity support
248 ******************************************************************************/
249
250static inline unsigned int read_id_aa64mmfr0_el0_tgran4_field(void)
251{
Andre Przywara0dda4242023-04-18 16:58:36 +0100252 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
253 ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100254}
255
256static inline unsigned int read_id_aa64mmfr0_el0_tgran16_field(void)
257{
258 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
Andre Przywara0dda4242023-04-18 16:58:36 +0100259 ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100260}
261
262static inline unsigned int read_id_aa64mmfr0_el0_tgran64_field(void)
263{
264 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(),
Andre Przywara0dda4242023-04-18 16:58:36 +0100265 ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
Javier Almansa Sobrino8c8107e2023-05-03 12:16:11 +0100266}
267
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000268static inline unsigned int read_feat_pmuv3_id_field(void)
269{
Andre Przywara0dda4242023-04-18 16:58:36 +0100270 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT);
Boyan Karatotev05504ba2023-02-15 13:21:50 +0000271}
272
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000273static inline unsigned int read_feat_mtpmu_id_field(void)
274{
Andre Przywara0dda4242023-04-18 16:58:36 +0100275 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT);
Boyan Karatotev677ed8a2023-02-16 09:45:29 +0000276}
277
278static inline bool is_feat_mtpmu_supported(void)
279{
280 if (DISABLE_MTPMU == FEAT_STATE_DISABLED) {
281 return false;
282 }
283
284 if (DISABLE_MTPMU == FEAT_STATE_ALWAYS) {
285 return true;
286 }
287
288 unsigned int mtpmu = read_feat_mtpmu_id_field();
289
290 return (mtpmu != 0U) && (mtpmu != ID_AA64DFR0_MTPMU_DISABLED);
291}
292
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000293#endif /* ARCH_FEATURES_H */