Jiafei Pan | f6954b1 | 2021-09-26 11:51:42 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2017-2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOC_H |
| 8 | #define SOC_H |
| 9 | |
| 10 | /* Chassis specific defines - common across SoC's of a particular platform */ |
| 11 | #include "dcfg_lsch2.h" |
| 12 | #include "soc_default_base_addr.h" |
| 13 | #include "soc_default_helper_macros.h" |
| 14 | |
| 15 | /* DDR Regions Info */ |
| 16 | #define NUM_DRAM_REGIONS 3 |
| 17 | #define NXP_DRAM0_ADDR 0x80000000 |
| 18 | #define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */ |
| 19 | |
| 20 | #define NXP_DRAM1_ADDR 0x880000000 |
| 21 | #define NXP_DRAM1_MAX_SIZE 0x780000000 /* 30 GB */ |
| 22 | |
| 23 | #define NXP_DRAM2_ADDR 0x8800000000 |
| 24 | #define NXP_DRAM2_MAX_SIZE 0x7800000000 /* 480 GB */ |
| 25 | /* DRAM0 Size defined in platform_def.h */ |
| 26 | #define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE |
| 27 | |
| 28 | /* |
| 29 | * P23: 23 x 23 package |
| 30 | * A: without security |
| 31 | * AE: with security |
| 32 | * SVR Definition (not include major and minor rev) |
| 33 | */ |
| 34 | #define SVR_LS1023A 0x879209 |
| 35 | #define SVR_LS1023AE 0x879208 |
| 36 | #define SVR_LS1023A_P23 0x87920B |
| 37 | #define SVR_LS1023AE_P23 0x87920A |
| 38 | #define SVR_LS1043A 0x879201 |
| 39 | #define SVR_LS1043AE 0x879200 |
| 40 | #define SVR_LS1043A_P23 0x879203 |
| 41 | #define SVR_LS1043AE_P23 0x879202 |
| 42 | |
| 43 | /* Number of cores in platform */ |
| 44 | #define PLATFORM_CORE_COUNT 4 |
| 45 | #define NUMBER_OF_CLUSTERS 1 |
| 46 | #define CORES_PER_CLUSTER 4 |
| 47 | |
| 48 | /* set to 0 if the clusters are not symmetrical */ |
| 49 | #define SYMMETRICAL_CLUSTERS 1 |
| 50 | |
| 51 | /* |
| 52 | * Required LS standard platform porting definitions |
| 53 | * for CCI-400 |
| 54 | */ |
| 55 | #define NXP_CCI_CLUSTER0_SL_IFACE_IX 4 |
| 56 | |
| 57 | /* ls1043 version info for GIC configuration */ |
| 58 | #define REV1_0 0x10 |
| 59 | #define REV1_1 0x11 |
| 60 | #define GIC_ADDR_BIT 31 |
| 61 | |
| 62 | /* Errata */ |
| 63 | #define NXP_ERRATUM_A009663 |
| 64 | #define NXP_ERRATUM_A009942 |
| 65 | |
| 66 | #define NUM_OF_DDRC 1 |
| 67 | |
| 68 | /* Defines required for using XLAT tables from ARM common code */ |
| 69 | #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40) |
| 70 | #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40) |
| 71 | |
| 72 | /* Clock Divisors */ |
| 73 | #define NXP_PLATFORM_CLK_DIVIDER 1 |
| 74 | #define NXP_UART_CLK_DIVIDER 1 |
| 75 | |
| 76 | /* |
| 77 | * Set this switch to 1 if you need to keep the debug block |
| 78 | * clocked during system power-down. |
| 79 | */ |
| 80 | #define DEBUG_ACTIVE 0 |
| 81 | |
| 82 | #define IPPDEXPCR_MAC1_1 0x80000000 // DEVDISR2_FMAN1_MAC1 |
| 83 | #define IPPDEXPCR_MAC1_2 0x40000000 // DEVDISR2_FMAN1_MAC2 |
| 84 | #define IPPDEXPCR_MAC1_3 0x20000000 // DEVDISR2_FMAN1_MAC3 |
| 85 | #define IPPDEXPCR_MAC1_4 0x10000000 // DEVDISR2_FMAN1_MAC4 |
| 86 | #define IPPDEXPCR_MAC1_5 0x08000000 // DEVDISR2_FMAN1_MAC5 |
| 87 | #define IPPDEXPCR_MAC1_6 0x04000000 // DEVDISR2_FMAN1_MAC6 |
| 88 | #define IPPDEXPCR_MAC1_9 0x00800000 // DEVDISR2_FMAN1_MAC9 |
| 89 | #define IPPDEXPCR_I2C1 0x00080000 // DEVDISR5_I2C_1 |
| 90 | #define IPPDEXPCR_LPUART1 0x00040000 // DEVDISR5_LPUART1 |
| 91 | #define IPPDEXPCR_FLX_TMR1 0x00020000 // DEVDISR5_FLX_TMR |
| 92 | #define IPPDEXPCR_OCRAM1 0x00010000 // DEVDISR5_OCRAM1 |
| 93 | #define IPPDEXPCR_GPIO1 0x00000040 // DEVDISR5_GPIO |
| 94 | #define IPPDEXPCR_FM1 0x00000008 // DEVDISR2_FMAN1 |
| 95 | |
| 96 | #define IPPDEXPCR_MASK1 0xFC800008 // overrides for DEVDISR2 |
| 97 | #define IPPDEXPCR_MASK2 0x000F0040 // overriddes for DEVDISR5 |
| 98 | |
| 99 | #define IPSTPCR0_VALUE 0xA000C201 |
| 100 | #define IPSTPCR1_VALUE 0x00000080 |
| 101 | #define IPSTPCR2_VALUE 0x000C0000 |
| 102 | #define IPSTPCR3_VALUE 0x38000000 |
| 103 | #if (DEBUG_ACTIVE) |
| 104 | #define IPSTPCR4_VALUE 0x10833BFC |
| 105 | #else |
| 106 | #define IPSTPCR4_VALUE 0x10A33BFC |
| 107 | #endif |
| 108 | |
| 109 | #define DEVDISR1_QE 0x00000001 |
| 110 | #define DEVDISR1_SEC 0x00000200 |
| 111 | #define DEVDISR1_USB1 0x00004000 |
| 112 | #define DEVDISR1_SATA 0x00008000 |
| 113 | #define DEVDISR1_USB2 0x00010000 |
| 114 | #define DEVDISR1_USB3 0x00020000 |
| 115 | #define DEVDISR1_DMA2 0x00400000 |
| 116 | #define DEVDISR1_DMA1 0x00800000 |
| 117 | #define DEVDISR1_ESDHC 0x20000000 |
| 118 | #define DEVDISR1_PBL 0x80000000 |
| 119 | |
| 120 | #define DEVDISR2_FMAN1 0x00000080 |
| 121 | #define DEVDISR2_FMAN1_MAC9 0x00800000 |
| 122 | #define DEVDISR2_FMAN1_MAC6 0x04000000 |
| 123 | #define DEVDISR2_FMAN1_MAC5 0x08000000 |
| 124 | #define DEVDISR2_FMAN1_MAC4 0x10000000 |
| 125 | #define DEVDISR2_FMAN1_MAC3 0x20000000 |
| 126 | #define DEVDISR2_FMAN1_MAC2 0x40000000 |
| 127 | #define DEVDISR2_FMAN1_MAC1 0x80000000 |
| 128 | |
| 129 | #define DEVDISR3_BMAN 0x00040000 |
| 130 | #define DEVDISR3_QMAN 0x00080000 |
| 131 | #define DEVDISR3_PEX3 0x20000000 |
| 132 | #define DEVDISR3_PEX2 0x40000000 |
| 133 | #define DEVDISR3_PEX1 0x80000000 |
| 134 | |
| 135 | #define DEVDISR4_QSPI 0x08000000 |
| 136 | #define DEVDISR4_DUART2 0x10000000 |
| 137 | #define DEVDISR4_DUART1 0x20000000 |
| 138 | |
| 139 | #define DEVDISR5_ICMMU 0x00000001 |
| 140 | #define DEVDISR5_I2C_1 0x00000002 |
| 141 | #define DEVDISR5_I2C_2 0x00000004 |
| 142 | #define DEVDISR5_I2C_3 0x00000008 |
| 143 | #define DEVDISR5_I2C_4 0x00000010 |
| 144 | #define DEVDISR5_WDG_5 0x00000020 |
| 145 | #define DEVDISR5_WDG_4 0x00000040 |
| 146 | #define DEVDISR5_WDG_3 0x00000080 |
| 147 | #define DEVDISR5_DSPI1 0x00000100 |
| 148 | #define DEVDISR5_WDG_2 0x00000200 |
| 149 | #define DEVDISR5_FLX_TMR 0x00000400 |
| 150 | #define DEVDISR5_WDG_1 0x00000800 |
| 151 | #define DEVDISR5_LPUART6 0x00001000 |
| 152 | #define DEVDISR5_LPUART5 0x00002000 |
| 153 | #define DEVDISR5_LPUART3 0x00008000 |
| 154 | #define DEVDISR5_LPUART2 0x00010000 |
| 155 | #define DEVDISR5_LPUART1 0x00020000 |
| 156 | #define DEVDISR5_DBG 0x00200000 |
| 157 | #define DEVDISR5_GPIO 0x00400000 |
| 158 | #define DEVDISR5_IFC 0x00800000 |
| 159 | #define DEVDISR5_OCRAM2 0x01000000 |
| 160 | #define DEVDISR5_OCRAM1 0x02000000 |
| 161 | #define DEVDISR5_LPUART4 0x10000000 |
| 162 | #define DEVDISR5_DDR 0x80000000 |
| 163 | #define DEVDISR5_MEM 0x80000000 |
| 164 | |
| 165 | #define DEVDISR1_VALUE 0xA0C3C201 |
| 166 | #define DEVDISR2_VALUE 0xCC0C0080 |
| 167 | #define DEVDISR3_VALUE 0xE00C0000 |
| 168 | #define DEVDISR4_VALUE 0x38000000 |
| 169 | #if (DEBUG_ACTIVE) |
| 170 | #define DEVDISR5_VALUE 0x10833BFC |
| 171 | #else |
| 172 | #define DEVDISR5_VALUE 0x10A33BFC |
| 173 | #endif |
| 174 | |
| 175 | /* |
| 176 | * PWR mgmt features supported in the soc-specific code: |
| 177 | * value == 0x0 the soc code does not support this feature |
| 178 | * value != 0x0 the soc code supports this feature |
| 179 | */ |
| 180 | #define SOC_CORE_RELEASE 0x1 |
| 181 | #define SOC_CORE_RESTART 0x1 |
| 182 | #define SOC_CORE_OFF 0x1 |
| 183 | #define SOC_CORE_STANDBY 0x1 |
| 184 | #define SOC_CORE_PWR_DWN 0x1 |
| 185 | #define SOC_CLUSTER_STANDBY 0x1 |
| 186 | #define SOC_CLUSTER_PWR_DWN 0x1 |
| 187 | #define SOC_SYSTEM_STANDBY 0x1 |
| 188 | #define SOC_SYSTEM_PWR_DWN 0x1 |
| 189 | #define SOC_SYSTEM_OFF 0x1 |
| 190 | #define SOC_SYSTEM_RESET 0x1 |
| 191 | |
| 192 | /* PSCI-specific defines */ |
| 193 | #define SYSTEM_PWR_DOMAINS 1 |
| 194 | #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ |
| 195 | NUMBER_OF_CLUSTERS + \ |
| 196 | SYSTEM_PWR_DOMAINS) |
| 197 | |
| 198 | /* Power state coordination occurs at the system level */ |
| 199 | #define PLAT_PD_COORD_LVL MPIDR_AFFLVL2 |
| 200 | #define PLAT_MAX_PWR_LVL PLAT_PD_COORD_LVL |
| 201 | |
| 202 | /* Local power state for power domains in Run state */ |
| 203 | #define LS_LOCAL_STATE_RUN PSCI_LOCAL_STATE_RUN |
| 204 | |
| 205 | /* define retention state */ |
| 206 | #define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1) |
| 207 | #define LS_LOCAL_STATE_RET PLAT_MAX_RET_STATE |
| 208 | |
| 209 | /* define power-down state */ |
| 210 | #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) |
| 211 | #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE |
| 212 | |
| 213 | /* |
| 214 | * Some data must be aligned on the biggest cache line size in the platform. |
| 215 | * This is known only to the platform as it might have a combination of |
| 216 | * integrated and external caches. |
| 217 | * CACHE_WRITEBACK_GRANULE is defined in soc.def |
| 218 | */ |
| 219 | |
| 220 | /* One cache line needed for bakery locks on ARM platforms */ |
| 221 | #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
| 222 | |
| 223 | #ifndef __ASSEMBLER__ |
| 224 | /* CCI slave interfaces */ |
| 225 | static const int cci_map[] = { |
| 226 | NXP_CCI_CLUSTER0_SL_IFACE_IX, |
| 227 | }; |
| 228 | void soc_init_lowlevel(void); |
| 229 | void soc_init_percpu(void); |
| 230 | void _soc_set_start_addr(unsigned long addr); |
| 231 | |
| 232 | #endif |
| 233 | |
| 234 | #endif /* SOC_H */ |