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git01.mediatek.com / filogic / atf / f68a084b460dc5afb360d4574b39246baa7d28d2 / . / plat / allwinner / common / allwinner-common.mk
blob: 901d888954d285bca1276b7afbc5fadffd980742 [file] [log] [blame]
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]1#
Samuel Holland1dad2652019-10-20 21:34:38 -0500[diff] [blame]2# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7include lib/xlat_tables_v2/xlat_tables.mk
Andre Przywara92b4c9b2020-08-03 00:25:03 +0100[diff] [blame]8include lib/libfdt/libfdt.mk
9include drivers/arm/gic/v2/gicv2.mk
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]10
11AW_PLAT := plat/allwinner
12
Samuel Holland4a024712019-11-27 13:09:40 -0600[diff] [blame]13PLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]14 -I${AW_PLAT}/common/include \
15 -I${AW_PLAT}/${PLAT}/include
16
Julius Werner6b88b652018-11-27 17:50:28 -0800[diff] [blame]17PLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]18 ${XLAT_TABLES_LIB_SRCS} \
19 ${AW_PLAT}/common/plat_helpers.S \
20 ${AW_PLAT}/common/sunxi_common.c
21
Samuel Holland1dad2652019-10-20 21:34:38 -0500[diff] [blame]22BL31_SOURCES += drivers/allwinner/axp/common.c \
Samuel Holland74703702018-10-21 12:24:16 -0500[diff] [blame]23 drivers/allwinner/sunxi_msgbox.c \
Samuel Holland103ee9b2018-10-21 12:41:03 -0500[diff] [blame]24 drivers/arm/css/scpi/css_scpi.c \
Andre Przywara92b4c9b2020-08-03 00:25:03 +0100[diff] [blame]25 ${GICV2_SOURCES} \
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]26 drivers/delay_timer/delay_timer.c \
27 drivers/delay_timer/generic_delay_timer.c \
28 lib/cpus/${ARCH}/cortex_a53.S \
29 plat/common/plat_gicv2.c \
30 plat/common/plat_psci_common.c \
31 ${AW_PLAT}/common/sunxi_bl31_setup.c \
32 ${AW_PLAT}/common/sunxi_cpu_ops.c \
33 ${AW_PLAT}/common/sunxi_pm.c \
34 ${AW_PLAT}/${PLAT}/sunxi_power.c \
35 ${AW_PLAT}/common/sunxi_security.c \
36 ${AW_PLAT}/common/sunxi_topology.c
37
38# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
39COLD_BOOT_SINGLE_CPU := 1
40
Samuel Hollandc47f00e2019-06-08 16:03:32 -0500[diff] [blame]41# Do not enable SPE (not supported on ARM v8.0).
42ENABLE_SPE_FOR_LOWER_ELS := 0
43
44# Do not enable SVE (not supported on ARM v8.0).
45ENABLE_SVE_FOR_NS := 0
46
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]47# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4.
48ERRATA_A53_835769 := 1
49ERRATA_A53_843419 := 1
50ERRATA_A53_855873 := 1
Samuel Holland3784ec92020-12-13 22:22:17 -0600[diff] [blame]51ERRATA_A53_1530924 := 1
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]52
Samuel Hollandafe21732020-12-13 20:05:11 -0600[diff] [blame]53# The traditional U-Boot load address is 160MB into DRAM.
54PRELOADED_BL33_BASE ?= 0x4a000000
55
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]56# The reset vector can be changed for each CPU.
57PROGRAMMABLE_RESET_ADDRESS := 1
58
59# Allow mapping read-only data as execute-never.
60SEPARATE_CODE_AND_RODATA := 1
61
Samuel Hollandd00eaa22019-10-27 14:07:52 -0500[diff] [blame]62# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
63SEPARATE_NOBITS_REGION := 1
64
Andre Przywara452b2b62018-09-28 00:37:19 +0100[diff] [blame]65# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
66RESET_TO_BL31 := 1
Andre Przywara647a2e12018-10-11 22:14:30 +0100[diff] [blame]67
Samuel Hollandc47f00e2019-06-08 16:03:32 -0500[diff] [blame]68# This platform is single-cluster and does not require coherency setup.
69WARMBOOT_ENABLE_DCACHE_EARLY := 1