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Varun Wadekarcd5a2f52015-09-20 15:08:22 +05301/*
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +01002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05305 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef MEMCTRL_V2_H
8#define MEMCTRL_V2_H
Varun Wadekarcd5a2f52015-09-20 15:08:22 +05309
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053010#include <tegra_def.h>
11
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053012#ifndef __ASSEMBLY__
13
Ambroise Vincentffbf32a2019-03-28 09:01:18 +000014#include <lib/mmio.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010015#include <stdint.h>
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053016
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053017/*******************************************************************************
Varun Wadekarc9ac3e42016-02-17 15:07:49 -080018 * Structure to hold the transaction override settings to use to override
19 * client inputs
20 ******************************************************************************/
21typedef struct mc_txn_override_cfg {
22 uint32_t offset;
23 uint8_t cgid_tag;
24} mc_txn_override_cfg_t;
25
26#define mc_make_txn_override_cfg(off, val) \
27 { \
28 .offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
29 .cgid_tag = MC_TXN_OVERRIDE_ ## val \
30 }
31
32/*******************************************************************************
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053033 * Structure to hold the Stream ID to use to override client inputs
34 ******************************************************************************/
35typedef struct mc_streamid_override_cfg {
36 uint32_t offset;
37 uint8_t stream_id;
38} mc_streamid_override_cfg_t;
39
40/*******************************************************************************
41 * Structure to hold the Stream ID Security Configuration settings
42 ******************************************************************************/
43typedef struct mc_streamid_security_cfg {
44 char *name;
45 uint32_t offset;
46 int override_enable;
47 int override_client_inputs;
48 int override_client_ns_flag;
49} mc_streamid_security_cfg_t;
50
Anthony Zhou0e07e452017-07-26 17:16:54 +080051#define OVERRIDE_DISABLE 1U
52#define OVERRIDE_ENABLE 0U
53#define CLIENT_FLAG_SECURE 0U
54#define CLIENT_FLAG_NON_SECURE 1U
55#define CLIENT_INPUTS_OVERRIDE 1U
56#define CLIENT_INPUTS_NO_OVERRIDE 0U
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053057/*******************************************************************************
58 * StreamID to indicate no SMMU translations (requests to be steered on the
59 * SMMU bypass path)
60 ******************************************************************************/
61#define MC_STREAM_ID_MAX 0x7FU
62
63/*******************************************************************************
64 * Memory Controller SMMU Bypass config register
65 ******************************************************************************/
66#define MC_SMMU_BYPASS_CONFIG 0x1820U
67#define MC_SMMU_BYPASS_CTRL_MASK 0x3U
68#define MC_SMMU_BYPASS_CTRL_SHIFT 0U
69#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT)
70#define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT)
71#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT)
72#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT)
73#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31)
74#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
75 MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
Varun Wadekarcd5a2f52015-09-20 15:08:22 +053076
77#define mc_make_sec_cfg(off, ns, ovrrd, access) \
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053078 { \
79 .name = # off, \
80 .offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
81 MC_STREAMID_OVERRIDE_CFG_ ## off), \
82 .override_client_ns_flag = CLIENT_FLAG_ ## ns, \
83 .override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
84 .override_enable = OVERRIDE_ ## access \
85 }
86
87/*******************************************************************************
88 * Structure to hold Memory Controller's Configuration settings
89 ******************************************************************************/
90typedef struct tegra_mc_settings {
91 const uint32_t *streamid_override_cfg;
92 uint32_t num_streamid_override_cfgs;
93 const mc_streamid_security_cfg_t *streamid_security_cfg;
94 uint32_t num_streamid_security_cfgs;
95 const mc_txn_override_cfg_t *txn_override_cfg;
96 uint32_t num_txn_override_cfgs;
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053097 void (*reconfig_mss_clients)(void);
98 void (*set_txn_overrides)(void);
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053099} tegra_mc_settings_t;
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530100
Varun Wadekarcd5a2f52015-09-20 15:08:22 +0530101static inline uint32_t tegra_mc_read_32(uint32_t off)
102{
103 return mmio_read_32(TEGRA_MC_BASE + off);
104}
105
106static inline void tegra_mc_write_32(uint32_t off, uint32_t val)
107{
108 mmio_write_32(TEGRA_MC_BASE + off, val);
109}
110
111static inline uint32_t tegra_mc_streamid_read_32(uint32_t off)
112{
113 return mmio_read_32(TEGRA_MC_STREAMID_BASE + off);
114}
115
116static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
117{
118 mmio_write_32(TEGRA_MC_STREAMID_BASE + off, val);
119}
120
Varun Wadekara0f26972016-03-11 17:18:51 -0800121#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
Anthony Zhou0e07e452017-07-26 17:16:54 +0800122 ((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
Varun Wadekara0f26972016-03-11 17:18:51 -0800123 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
124
Krishna Reddy329e2282017-05-25 11:04:33 -0700125#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
126 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
Varun Wadekara0f26972016-03-11 17:18:51 -0800127
128#define mc_set_tsa_passthrough(client) \
129 { \
130 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
131 (TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
Anthony Zhou0844b972017-06-28 16:35:54 +0800132 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
133 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
Varun Wadekara0f26972016-03-11 17:18:51 -0800134 }
135
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530136#define mc_set_tsa_w_passthrough(client) \
137 { \
138 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
139 (TSA_CONFIG_STATIC0_CSW_RESET_W & \
140 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
141 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
142 }
143
144#define mc_set_tsa_r_passthrough(client) \
145 { \
146 mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
147 (TSA_CONFIG_STATIC0_CSR_RESET_R & \
148 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
149 (uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
150 }
151
Krishna Reddy329e2282017-05-25 11:04:33 -0700152#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
Varun Wadekara0f26972016-03-11 17:18:51 -0800153 { \
154 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
Krishna Reddy329e2282017-05-25 11:04:33 -0700155 MC_TXN_OVERRIDE_##normal_axi_id | \
156 MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
157 MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
158 MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
Varun Wadekara0f26972016-03-11 17:18:51 -0800159 }
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530160
161/*******************************************************************************
162 * Handler to read memory configuration settings
163 *
164 * Implemented by SoCs under tegra/soc/txxx
165 ******************************************************************************/
166tegra_mc_settings_t *tegra_get_mc_settings(void);
167
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700168/*******************************************************************************
169 * Handler to program the scratch registers with TZDRAM settings for the
170 * resume firmware.
171 *
172 * Implemented by SoCs under tegra/soc/txxx
173 ******************************************************************************/
174void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes);
175
176#endif /* __ASSEMBLY__ */
Varun Wadekara0f26972016-03-11 17:18:51 -0800177
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000178#endif /* MEMCTRL_V2_H */