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git01.mediatek.com / filogic / atf / f558cac26b4485a6b34bcfd325fbd4cc698663ce / . / bl2 / aarch64 / bl2_entrypoint.S
blob: 09eadff2e08eeea6b3e886352a11460ec53e847f [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleye83b0ca2014-01-14 18:17:09 +0000[diff] [blame]2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]31#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]32#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +0100[diff] [blame]33#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]34
35
36 .globl bl2_entrypoint
37
38
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]39
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]40func bl2_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]41 /*---------------------------------------------
42 * Store the extents of the tzram available to
43 * BL2 for future use. Use the opcode param to
44 * allow implement other functions if needed.
45 * ---------------------------------------------
46 */
47 mov x20, x0
48 mov x21, x1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]49
50 /* ---------------------------------------------
51 * This is BL2 which is expected to be executed
52 * only by the primary cpu (at least for now).
53 * So, make sure no secondary has lost its way.
54 * ---------------------------------------------
55 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100[diff] [blame]56 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]57 bl platform_is_primary_cpu
58 cbz x0, _panic
59
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]60 /* ---------------------------------------------
61 * Set the exception vector to something sane.
62 * ---------------------------------------------
63 */
64 adr x0, early_exceptions
65 msr vbar_el1, x0
66
67 /* ---------------------------------------------
68 * Enable the instruction cache.
69 * ---------------------------------------------
70 */
71 mrs x0, sctlr_el1
72 orr x0, x0, #SCTLR_I_BIT
73 msr sctlr_el1, x0
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]74 isb
75
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]76 /* ---------------------------------------------
Sandrine Bailleux34edaed2013-12-02 15:45:07 +0000[diff] [blame]77 * Check the opcodes out of paranoia.
78 * ---------------------------------------------
79 */
80 mov x0, #RUN_IMAGE
81 cmp x0, x20
82 b.ne _panic
83
84 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]85 * Zero out NOBITS sections. There are 2 of them:
86 * - the .bss section;
87 * - the coherent memory section.
88 * ---------------------------------------------
89 */
90 ldr x0, =__BSS_START__
91 ldr x1, =__BSS_SIZE__
92 bl zeromem16
93
94 ldr x0, =__COHERENT_RAM_START__
95 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
96 bl zeromem16
97
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]98 /* --------------------------------------------
99 * Give ourselves a small coherent stack to
100 * ease the pain of initializing the MMU
101 * --------------------------------------------
102 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100[diff] [blame]103 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]104 bl platform_set_coherent_stack
105
106 /* ---------------------------------------------
107 * Perform early platform setup & platform
108 * specific early arch. setup e.g. mmu setup
109 * ---------------------------------------------
110 */
111 mov x0, x21
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]112 bl bl2_early_platform_setup
113 bl bl2_plat_arch_setup
114
115 /* ---------------------------------------------
116 * Give ourselves a stack allocated in Normal
117 * -IS-WBWA memory
118 * ---------------------------------------------
119 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100[diff] [blame]120 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]121 bl platform_set_stack
122
123 /* ---------------------------------------------
124 * Jump to main function.
125 * ---------------------------------------------
126 */
127 bl bl2_main
128_panic:
129 b _panic