blob: 6e48e31389775f05ab249c36f7fa2ddeae0dc307 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000031#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +000032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <bl_common.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35 .globl bl31_entrypoint
36
37
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 /* -----------------------------------------------------
39 * bl31_entrypoint() is the cold boot entrypoint,
40 * executed only by the primary cpu.
41 * -----------------------------------------------------
42 */
43
Andrew Thoelke38bde412014-03-18 13:46:55 +000044func bl31_entrypoint
Vikram Kanigirida567432014-04-15 18:08:08 +010045 /* ---------------------------------------------------------------
46 * Preceding bootloader has populated x0 with a pointer to a
47 * 'bl31_params' structure & x1 with a pointer to platform
48 * specific structure
49 * ---------------------------------------------------------------
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000050 */
Vikram Kanigiri96377452014-04-24 11:02:16 +010051#if !RESET_TO_BL31
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052 mov x20, x0
53 mov x21, x1
Vikram Kanigiri96377452014-04-24 11:02:16 +010054#else
55
56 /* -----------------------------------------------------
57 * Perform any processor specific actions upon reset
58 * e.g. cache, tlb invalidations etc. Override the
59 * Boot ROM(BL0) programming sequence
60 * -----------------------------------------------------
61 */
62 bl cpu_reset_handler
63#endif
64
65 /* ---------------------------------------------
66 * Enable the instruction cache.
67 * ---------------------------------------------
68 */
69 mrs x1, sctlr_el3
70 orr x1, x1, #SCTLR_I_BIT
71 msr sctlr_el3, x1
72 isb
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000073
74 /* ---------------------------------------------
Andrew Thoelke4d2d5532014-06-02 12:38:12 +010075 * Set the exception vector and zero tpidr_el3
76 * until the crash reporting is set up
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000077 * ---------------------------------------------
78 */
Andrew Thoelke4d2d5532014-06-02 12:38:12 +010079 adr x1, runtime_exceptions
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000080 msr vbar_el3, x1
Andrew Thoelke4d2d5532014-06-02 12:38:12 +010081 msr tpidr_el3, xzr
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +000082
Harry Liebel4f603682014-01-14 18:11:48 +000083 /* ---------------------------------------------------------------------
84 * The initial state of the Architectural feature trap register
85 * (CPTR_EL3) is unknown and it must be set to a known state. All
86 * feature traps are disabled. Some bits in this register are marked as
87 * Reserved and should not be modified.
88 *
89 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
90 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
91 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
92 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
93 * access to trace functionality is not supported, this bit is RES0.
94 * CPTR_EL3.TFP: This causes instructions that access the registers
95 * associated with Floating Point and Advanced SIMD execution to trap
96 * to EL3 when executed from any exception level, unless trapped to EL1
97 * or EL2.
98 * ---------------------------------------------------------------------
99 */
100 mrs x1, cptr_el3
101 bic w1, w1, #TCPAC_BIT
102 bic w1, w1, #TTA_BIT
103 bic w1, w1, #TFP_BIT
104 msr cptr_el3, x1
105
Vikram Kanigiri96377452014-04-24 11:02:16 +0100106#if RESET_TO_BL31
Vikram Kanigiricf79bf52014-06-02 14:59:00 +0100107 /* -------------------------------------------------------
108 * Will not return from this macro if it is a warm boot.
109 * -------------------------------------------------------
110 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100111 wait_for_entrypoint
112 bl platform_mem_init
113#else
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000114 /* ---------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115 * This is BL31 which is expected to be executed
116 * only by the primary cpu (at least for now).
117 * So, make sure no secondary has lost its way.
118 * ---------------------------------------------
119 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100120 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 bl platform_is_primary_cpu
122 cbz x0, _panic
Vikram Kanigiri96377452014-04-24 11:02:16 +0100123#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100124
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000125 /* ---------------------------------------------
126 * Zero out NOBITS sections. There are 2 of them:
127 * - the .bss section;
128 * - the coherent memory section.
129 * ---------------------------------------------
130 */
131 ldr x0, =__BSS_START__
132 ldr x1, =__BSS_SIZE__
133 bl zeromem16
134
135 ldr x0, =__COHERENT_RAM_START__
136 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
137 bl zeromem16
138
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000139 /* ---------------------------------------------
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100140 * Initialise cpu_data and crash reporting
141 * ---------------------------------------------
142 */
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100143#if CRASH_REPORTING
144 bl init_crash_reporting
145#endif
Andrew Thoelke4d2d5532014-06-02 12:38:12 +0100146 bl init_cpu_data_ptr
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100147
148 /* ---------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000149 * Use SP_EL0 for the C runtime stack.
150 * ---------------------------------------------
151 */
152 msr spsel, #0
153
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154 /* --------------------------------------------
155 * Give ourselves a small coherent stack to
156 * ease the pain of initializing the MMU
157 * --------------------------------------------
158 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100159 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160 bl platform_set_coherent_stack
161
162 /* ---------------------------------------------
163 * Perform platform specific early arch. setup
164 * ---------------------------------------------
165 */
Vikram Kanigiri96377452014-04-24 11:02:16 +0100166#if RESET_TO_BL31
167 mov x0, 0
168 mov x1, 0
169#else
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170 mov x0, x20
171 mov x1, x21
Vikram Kanigiri96377452014-04-24 11:02:16 +0100172#endif
173
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 bl bl31_early_platform_setup
175 bl bl31_plat_arch_setup
176
177 /* ---------------------------------------------
178 * Give ourselves a stack allocated in Normal
179 * -IS-WBWA memory
180 * ---------------------------------------------
181 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100182 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100183 bl platform_set_stack
184
185 /* ---------------------------------------------
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000186 * Jump to main function.
Achin Guptab739f222014-01-18 16:50:09 +0000187 * ---------------------------------------------
188 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000189 bl bl31_main
Achin Guptab739f222014-01-18 16:50:09 +0000190
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000191 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192
193_panic:
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000194 wfi
Achin Gupta4f6ad662013-10-25 09:08:21 +0100195 b _panic