blob: 92bf484729bbd8f6675b8d47512e67419cb48a0f [file] [log] [blame]
Gary Morrison3d7f6542021-01-27 13:08:47 -06001/*
2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef FVP_R_ARCH_HELPERS_H
8#define FVP_R_ARCH_HELPERS_H
9
10#include <arch_helpers.h>
11
12/*******************************************************************************
13 * MPU register definitions
14 ******************************************************************************/
15#define MPUIR_EL2 S3_4_C0_C0_4
16#define PRBAR_EL2 S3_4_C6_C8_0
17#define PRLAR_EL2 S3_4_C6_C8_1
18#define PRSELR_EL2 S3_4_C6_C2_1
19#define PRENR_EL2 S3_4_C6_C1_1
20
21/* v8-R64 MPU registers */
22DEFINE_RENAME_SYSREG_RW_FUNCS(mpuir_el2, MPUIR_EL2)
23DEFINE_RENAME_SYSREG_RW_FUNCS(prenr_el2, PRENR_EL2)
24DEFINE_RENAME_SYSREG_RW_FUNCS(prselr_el2, PRSELR_EL2)
25DEFINE_RENAME_SYSREG_RW_FUNCS(prbar_el2, PRBAR_EL2)
26DEFINE_RENAME_SYSREG_RW_FUNCS(prlar_el2, PRLAR_EL2)
27
28#endif /* FVP_R_ARCH_HELPERS_H */