blob: 8f0bc62bce13b19275b3241396f111c1774646e6 [file] [log] [blame]
Roberto Vargase92111a2018-05-22 16:05:42 +01001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <platform_def.h>
8#include <xlat_tables_defs.h>
9
10MEMORY {
11 ROM (rx): ORIGIN = ROMLIB_RO_BASE, LENGTH = ROMLIB_RO_LIMIT - ROMLIB_RO_BASE
12 RAM (rwx): ORIGIN = ROMLIB_RW_BASE, LENGTH = ROMLIB_RW_END - ROMLIB_RW_BASE
13}
14
15OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
16OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
17ENTRY(jmptbl)
18
19SECTIONS
20{
21 . = ROMLIB_RO_BASE;
22 .text : {
23 *jmptbl.o(.text)
24 *(.text*)
25 *(.rodata*)
26 } >ROM
27
28 __DATA_ROM_START__ = LOADADDR(.data);
29
30 .data : {
31 __DATA_RAM_START__ = .;
32 *(.data*)
33 __DATA_RAM_END__ = .;
34 } >RAM AT>ROM
35
36 __DATA_SIZE__ = SIZEOF(.data);
37
38 .bss : {
39 __BSS_START__ = .;
40 *(.bss*)
41 __BSS_END__ = .;
42 } >RAM
43 __BSS_SIZE__ = SIZEOF(.bss);
44}