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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorovf41355c2019-09-13 14:11:59 +01002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <stddef.h>
9
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010011#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <common/bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010013#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/el3_runtime/context_mgmt.h>
15#include <lib/cpus/errata_report.h>
16#include <plat/common/platform.h>
17
Dan Handley714a0d22014-04-09 13:13:04 +010018#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
20/*******************************************************************************
Achin Guptaef7a28c2014-02-01 08:59:56 +000021 * Per cpu non-secure contexts used to program the architectural state prior
22 * return to the normal world.
23 * TODO: Use the memory allocator to set aside memory for the contexts instead
Soby Mathew981487a2015-07-13 14:10:57 +010024 * of relying on platform defined constants.
Achin Guptaef7a28c2014-02-01 08:59:56 +000025 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +010026static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
Achin Guptaef7a28c2014-02-01 08:59:56 +000027
Soby Mathew6cdddaf2015-01-07 11:10:22 +000028/******************************************************************************
29 * Define the psci capability variable.
30 *****************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010031unsigned int psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +000032
Dan Handley60b13e32014-05-14 15:13:16 +010033/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010034 * Function which initializes the 'psci_non_cpu_pd_nodes' or the
35 * 'psci_cpu_pd_nodes' corresponding to the power level.
Achin Gupta4f6ad662013-10-25 09:08:21 +010036 ******************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +010037static void __init psci_init_pwr_domain_node(unsigned char node_idx,
Soby Mathew011ca182015-07-29 17:05:03 +010038 unsigned int parent_idx,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010039 unsigned char level)
Achin Gupta4f6ad662013-10-25 09:08:21 +010040{
Soby Mathew981487a2015-07-13 14:10:57 +010041 if (level > PSCI_CPU_PWR_LVL) {
42 psci_non_cpu_pd_nodes[node_idx].level = level;
43 psci_lock_init(psci_non_cpu_pd_nodes, node_idx);
44 psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx;
45 psci_non_cpu_pd_nodes[node_idx].local_state =
46 PLAT_MAX_OFF_STATE;
47 } else {
48 psci_cpu_data_t *svc_cpu_data;
Achin Gupta4f6ad662013-10-25 09:08:21 +010049
Soby Mathew981487a2015-07-13 14:10:57 +010050 psci_cpu_pd_nodes[node_idx].parent_node = parent_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +010051
Soby Mathew981487a2015-07-13 14:10:57 +010052 /* Initialize with an invalid mpidr */
53 psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR;
Soby Mathew2b697502014-10-02 17:24:19 +010054
Soby Mathew981487a2015-07-13 14:10:57 +010055 svc_cpu_data =
56 &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data);
Soby Mathew2b697502014-10-02 17:24:19 +010057
Soby Mathew981487a2015-07-13 14:10:57 +010058 /* Set the Affinity Info for the cores as OFF */
59 svc_cpu_data->aff_info_state = AFF_STATE_OFF;
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Soby Mathew981487a2015-07-13 14:10:57 +010061 /* Invalidate the suspend level for the cpu */
Soby Mathew011ca182015-07-29 17:05:03 +010062 svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +010063
Soby Mathew981487a2015-07-13 14:10:57 +010064 /* Set the power state to OFF state */
65 svc_cpu_data->local_state = PLAT_MAX_OFF_STATE;
Soby Mathew2b697502014-10-02 17:24:19 +010066
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +000067 psci_flush_dcache_range((uintptr_t)svc_cpu_data,
Soby Mathew981487a2015-07-13 14:10:57 +010068 sizeof(*svc_cpu_data));
Achin Gupta4f6ad662013-10-25 09:08:21 +010069
Soby Mathew981487a2015-07-13 14:10:57 +010070 cm_set_context_by_index(node_idx,
71 (void *) &psci_ns_context[node_idx],
72 NON_SECURE);
73 }
Achin Gupta4f6ad662013-10-25 09:08:21 +010074}
75
76/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +010077 * This functions updates cpu_start_idx and ncpus field for each of the node in
78 * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of
79 * the CPUs and check whether they match with the parent of the previous
80 * CPU. The basic assumption for this work is that children of the same parent
81 * are allocated adjacent indices. The platform should ensure this though proper
82 * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and
83 * plat_my_core_pos() APIs.
84 *******************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +010085static void __init psci_update_pwrlvl_limits(void)
Achin Gupta0959db52013-12-02 17:33:04 +000086{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010087 int j, cpu_idx;
Soby Mathew981487a2015-07-13 14:10:57 +010088 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0};
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010089 unsigned int temp_index[PLAT_MAX_PWR_LVL];
Achin Gupta0959db52013-12-02 17:33:04 +000090
Soby Mathew981487a2015-07-13 14:10:57 +010091 for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
92 psci_get_parent_pwr_domain_nodes(cpu_idx,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010093 (unsigned int)PLAT_MAX_PWR_LVL,
Soby Mathew981487a2015-07-13 14:10:57 +010094 temp_index);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +010095 for (j = (int) PLAT_MAX_PWR_LVL - 1; j >= 0; j--) {
Soby Mathew981487a2015-07-13 14:10:57 +010096 if (temp_index[j] != nodes_idx[j]) {
97 nodes_idx[j] = temp_index[j];
98 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx
99 = cpu_idx;
Achin Gupta0959db52013-12-02 17:33:04 +0000100 }
Soby Mathew981487a2015-07-13 14:10:57 +0100101 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++;
102 }
Achin Gupta0959db52013-12-02 17:33:04 +0000103 }
Achin Gupta0959db52013-12-02 17:33:04 +0000104}
105
106/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100107 * Core routine to populate the power domain tree. The tree descriptor passed by
108 * the platform is populated breadth-first and the first entry in the map
109 * informs the number of root power domains. The parent nodes of the root nodes
110 * will point to an invalid entry(-1).
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 ******************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +0100112static void __init populate_power_domain_tree(const unsigned char *topology)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100114 unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl;
115 unsigned int node_index = 0U, num_children;
116 int parent_node_index = 0;
117 int level = (int) PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118
119 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100120 * For each level the inputs are:
121 * - number of nodes at this level in plat_array i.e. num_nodes_at_level
122 * This is the sum of values of nodes at the parent level.
123 * - Index of first entry at this level in the plat_array i.e.
124 * parent_node_index.
125 * - Index of first free entry in psci_non_cpu_pd_nodes[] or
126 * psci_cpu_pd_nodes[] i.e. node_index depending upon the level.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100128 while (level >= (int) PSCI_CPU_PWR_LVL) {
129 num_nodes_at_next_lvl = 0U;
Achin Guptaef7a28c2014-02-01 08:59:56 +0000130 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100131 * For each entry (parent node) at this level in the plat_array:
132 * - Find the number of children
133 * - Allocate a node in a power domain array for each child
134 * - Set the parent of the child to the parent_node_index - 1
135 * - Increment parent_node_index to point to the next parent
136 * - Accumulate the number of children at next level.
Achin Guptaef7a28c2014-02-01 08:59:56 +0000137 */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100138 for (i = 0U; i < num_nodes_at_lvl; i++) {
Soby Mathew981487a2015-07-13 14:10:57 +0100139 assert(parent_node_index <=
140 PSCI_NUM_NON_CPU_PWR_DOMAINS);
141 num_children = topology[parent_node_index];
Achin Guptaef7a28c2014-02-01 08:59:56 +0000142
Soby Mathew981487a2015-07-13 14:10:57 +0100143 for (j = node_index;
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100144 j < (node_index + num_children); j++)
145 psci_init_pwr_domain_node((unsigned char)j,
Soby Mathew981487a2015-07-13 14:10:57 +0100146 parent_node_index - 1,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100147 (unsigned char)level);
Achin Guptaf3ccbab2014-07-25 14:52:47 +0100148
Soby Mathew981487a2015-07-13 14:10:57 +0100149 node_index = j;
150 num_nodes_at_next_lvl += num_children;
151 parent_node_index++;
152 }
Achin Guptaf6b9e992014-07-31 11:19:11 +0100153
Soby Mathew981487a2015-07-13 14:10:57 +0100154 num_nodes_at_lvl = num_nodes_at_next_lvl;
155 level--;
Soby Mathew7d861ea2014-11-18 10:14:14 +0000156
Soby Mathew981487a2015-07-13 14:10:57 +0100157 /* Reset the index for the cpu power domain array */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100158 if (level == (int) PSCI_CPU_PWR_LVL)
Soby Mathew981487a2015-07-13 14:10:57 +0100159 node_index = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100160 }
161
Soby Mathew981487a2015-07-13 14:10:57 +0100162 /* Validate the sanity of array exported by the platform */
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100163 assert((int) j == PLATFORM_CORE_COUNT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164}
165
166/*******************************************************************************
Soby Mathewd0194872016-04-29 19:01:30 +0100167 * This function does the architectural setup and takes the warm boot
168 * entry-point `mailbox_ep` as an argument. The function also initializes the
169 * power domain topology tree by querying the platform. The power domain nodes
170 * higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and
171 * the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform
172 * exports its static topology map through the
Soby Mathew981487a2015-07-13 14:10:57 +0100173 * populate_power_domain_topology_tree() API. The algorithm populates the
174 * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this
Soby Mathewd0194872016-04-29 19:01:30 +0100175 * topology map. On a platform that implements two clusters of 2 cpus each,
176 * and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would
177 * look like this:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178 *
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179 * ---------------------------------------------------
Soby Mathew981487a2015-07-13 14:10:57 +0100180 * | system node | cluster 0 node | cluster 1 node |
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181 * ---------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182 *
Soby Mathew981487a2015-07-13 14:10:57 +0100183 * And populated psci_cpu_pd_nodes would look like this :
184 * <- cpus cluster0 -><- cpus cluster1 ->
185 * ------------------------------------------------
186 * | CPU 0 | CPU 1 | CPU 2 | CPU 3 |
187 * ------------------------------------------------
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 ******************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +0100189int __init psci_setup(const psci_lib_args_t *lib_args)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100190{
Soby Mathew981487a2015-07-13 14:10:57 +0100191 const unsigned char *topology_tree;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192
Soby Mathew89256b82016-09-13 14:19:08 +0100193 assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args));
194
Soby Mathewd0194872016-04-29 19:01:30 +0100195 /* Do the Architectural initialization */
196 psci_arch_setup();
197
Soby Mathew981487a2015-07-13 14:10:57 +0100198 /* Query the topology map from the platform */
199 topology_tree = plat_get_power_domain_tree_desc();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200
Soby Mathew981487a2015-07-13 14:10:57 +0100201 /* Populate the power domain arrays using the platform topology map */
202 populate_power_domain_tree(topology_tree);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100203
Soby Mathew981487a2015-07-13 14:10:57 +0100204 /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
205 psci_update_pwrlvl_limits();
206
207 /* Populate the mpidr field of cpu node for this CPU */
208 psci_cpu_pd_nodes[plat_my_core_pos()].mpidr =
209 read_mpidr() & MPIDR_AFFINITY_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210
Soby Mathew981487a2015-07-13 14:10:57 +0100211 psci_init_req_local_pwr_states();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212
213 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100214 * Set the requested and target state of this CPU and all the higher
215 * power domain levels for this CPU to run.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216 */
Soby Mathew981487a2015-07-13 14:10:57 +0100217 psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100218
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100219 (void) plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep,
220 &psci_plat_pm_ops);
221 assert(psci_plat_pm_ops != NULL);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222
Soby Mathew7c9d5f82016-09-09 11:33:58 +0100223 /*
224 * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000225 * during warm boot, possibly before data cache is enabled.
Soby Mathew7c9d5f82016-09-09 11:33:58 +0100226 */
Jeenu Viswambharan0b56d6f2017-01-06 14:58:11 +0000227 psci_flush_dcache_range((uintptr_t)&psci_plat_pm_ops,
Soby Mathew7c9d5f82016-09-09 11:33:58 +0100228 sizeof(psci_plat_pm_ops));
229
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000230 /* Initialize the psci capability */
231 psci_caps = PSCI_GENERIC_CAP;
232
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100233 if (psci_plat_pm_ops->pwr_domain_off != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000234 psci_caps |= define_psci_cap(PSCI_CPU_OFF);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100235 if ((psci_plat_pm_ops->pwr_domain_on != NULL) &&
236 (psci_plat_pm_ops->pwr_domain_on_finish != NULL))
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000237 psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100238 if ((psci_plat_pm_ops->pwr_domain_suspend != NULL) &&
239 (psci_plat_pm_ops->pwr_domain_suspend_finish != NULL)) {
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000240 psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100241 if (psci_plat_pm_ops->get_sys_suspend_power_state != NULL)
Soby Mathew96168382014-12-17 14:47:57 +0000242 psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);
243 }
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100244 if (psci_plat_pm_ops->system_off != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000245 psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100246 if (psci_plat_pm_ops->system_reset != NULL)
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000247 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100248 if (psci_plat_pm_ops->get_node_hw_state != NULL)
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +0100249 psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100250 if ((psci_plat_pm_ops->read_mem_protect != NULL) &&
251 (psci_plat_pm_ops->write_mem_protect != NULL))
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100252 psci_caps |= define_psci_cap(PSCI_MEM_PROTECT);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100253 if (psci_plat_pm_ops->mem_protect_chk != NULL)
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100254 psci_caps |= define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64);
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100255 if (psci_plat_pm_ops->system_reset2 != NULL)
Roberto Vargasb820ad02017-07-26 09:23:09 +0100256 psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64);
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000257
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100258#if ENABLE_PSCI_STAT
259 psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64);
260 psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64);
261#endif
262
Achin Gupta7421b462014-02-01 18:53:26 +0000263 return 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264}
Soby Mathewd0194872016-04-29 19:01:30 +0100265
266/*******************************************************************************
267 * This duplicates what the primary cpu did after a cold boot in BL1. The same
268 * needs to be done when a cpu is hotplugged in. This function could also over-
269 * ride any EL3 setup done by BL1 as this code resides in rw memory.
270 ******************************************************************************/
271void psci_arch_setup(void)
272{
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100273#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
Soby Mathewd0194872016-04-29 19:01:30 +0100274 /* Program the counter frequency */
275 write_cntfrq_el0(plat_get_syscnt_freq2());
Etienne Carrieree259fa72017-11-08 14:41:47 +0100276#endif
Soby Mathewd0194872016-04-29 19:01:30 +0100277
278 /* Initialize the cpu_ops pointer. */
279 init_cpu_ops();
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000280
281 /* Having initialized cpu_ops, we can now print errata status */
282 print_errata_status();
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100283
284#if ENABLE_PAUTH
285 /* Store APIAKey_EL1 key */
286 set_cpu_data(apiakey[0], read_apiakeylo_el1());
287 set_cpu_data(apiakey[1], read_apiakeyhi_el1());
288#endif /* ENABLE_PAUTH */
Soby Mathewd0194872016-04-29 19:01:30 +0100289}
Soby Mathew89d90dc2016-05-05 14:11:23 +0100290
291/******************************************************************************
292 * PSCI Library interface to initialize the cpu context for the next non
293 * secure image during cold boot. The relevant registers in the cpu context
294 * need to be retrieved and programmed on return from this interface.
295 *****************************************************************************/
296void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info)
297{
298 assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE);
299 cm_init_my_context(next_image_info);
300 cm_prepare_el3_exit(NON_SECURE);
301}