blob: fa69be2e6f49911da74ebd66acc6e86e630f97ff [file] [log] [blame]
Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +00007#include <common/bl_common.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/debug.h>
9
Jiafei Pan46367ad2018-03-02 07:23:30 +000010#include "ls_16550.h"
11#include "plat_ls.h"
Jiafei Pan46367ad2018-03-02 07:23:30 +000012
13/* Data structure which holds the extents of the trusted SRAM for BL1*/
14static meminfo_t bl1_tzram_layout;
15
16meminfo_t *bl1_plat_sec_mem_layout(void)
17{
18 return &bl1_tzram_layout;
19}
20
21/*******************************************************************************
22 * BL1 specific platform actions shared between ARM standard platforms.
23 ******************************************************************************/
24void ls_bl1_early_platform_setup(void)
25{
Andre Przywara15069ea2020-01-25 00:58:35 +000026 static console_t console;
Jiafei Pan46367ad2018-03-02 07:23:30 +000027
28#if !LS1043_DISABLE_TRUSTED_WDOG
29 /* TODO: Enable watchdog */
30
31#endif
32
33 /* Initialize the console to provide early debug support */
34 console_ls_16550_register(LS_TF_UART_BASE, LS_TF_UART_CLOCK,
35 LS_TF_UART_BAUDRATE, &console);
36
37 /* Allow BL1 to see the whole Trusted RAM */
38 bl1_tzram_layout.total_base = LS_SRAM_BASE;
39 bl1_tzram_layout.total_size = LS_SRAM_SIZE;
40}
41
42/******************************************************************************
43 * Perform the very early platform specific architecture setup shared between
44 * ARM standard platforms. This only does basic initialization. Later
45 * architectural setup (bl1_arch_setup()) does not do anything platform
46 * specific.
47 *****************************************************************************/
48void ls_bl1_plat_arch_setup(void)
49{
50 ls_setup_page_tables(bl1_tzram_layout.total_base,
51 bl1_tzram_layout.total_size,
52 BL_CODE_BASE,
53 BL1_CODE_END,
54 BL1_RO_DATA_BASE,
55 BL1_RO_DATA_END
56#if USE_COHERENT_MEM
57 , BL_COHERENT_RAM_BASE,
58 BL_COHERENT_RAM_END
59#endif
60 );
61 VERBOSE("After setup the page tables\n");
Julius Werner8e0ef0f2019-07-09 14:02:43 -070062#ifdef __aarch64__
Jiafei Pan46367ad2018-03-02 07:23:30 +000063 enable_mmu_el3(0);
Julius Werner8e0ef0f2019-07-09 14:02:43 -070064#else
65 enable_mmu_svc_mon(0);
66#endif /* __aarch64__ */
Jiafei Pan46367ad2018-03-02 07:23:30 +000067 VERBOSE("After MMU enabled\n");
68}
69
70void bl1_plat_arch_setup(void)
71{
72 ls_bl1_plat_arch_setup();
73}
74
75/*
76 * Perform the platform specific architecture setup shared between
77 * ARM standard platforms.
78 */
79void ls_bl1_platform_setup(void)
80{
81 /* Initialise the IO layer and register platform IO devices */
82 plat_ls_io_setup();
83}
84
85void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
86{
87#if !LS1043_DISABLE_TRUSTED_WDOG
88 /*TODO: Disable watchdog before leaving BL1 */
89#endif
90}