blob: 76200eca01f00e91ef75fb0f15fd770c941f6749 [file] [log] [blame]
developer65014b82015-04-13 14:47:57 +08001/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
developer65014b82015-04-13 14:47:57 +08005 */
developereee29802016-05-11 18:45:20 +08006#include <crypt.h>
developer73b982f2016-05-11 18:04:09 +08007#include <debug.h>
developer65014b82015-04-13 14:47:57 +08008#include <mmio.h>
9#include <mtk_sip_svc.h>
developerb8925a22015-11-16 14:38:40 +080010#include <mtcmos.h>
developer73b982f2016-05-11 18:04:09 +080011#include <plat_sip_calls.h>
12#include <runtime_svc.h>
developer65014b82015-04-13 14:47:57 +080013
14/* Authorized secure register list */
15enum {
16 SREG_HDMI_COLOR_EN = 0x14000904
17};
18
19static const uint32_t authorized_sreg[] = {
20 SREG_HDMI_COLOR_EN
21};
22
23#define authorized_sreg_cnt \
24 (sizeof(authorized_sreg) / sizeof(authorized_sreg[0]))
25
26uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val)
27{
28 uint64_t i;
29
30 for (i = 0; i < authorized_sreg_cnt; i++) {
31 if (authorized_sreg[i] == sreg) {
32 mmio_write_32(sreg, val);
33 return MTK_SIP_E_SUCCESS;
34 }
35 }
36
37 return MTK_SIP_E_INVALID_PARAM;
38}
developerb8925a22015-11-16 14:38:40 +080039
developer73b982f2016-05-11 18:04:09 +080040static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val)
developerb8925a22015-11-16 14:38:40 +080041{
42 uint32_t ret;
43
44 ret = mtcmos_non_cpu_ctrl(1, val);
45 if (ret)
46 return MTK_SIP_E_INVALID_PARAM;
47 else
48 return MTK_SIP_E_SUCCESS;
49}
50
developer73b982f2016-05-11 18:04:09 +080051static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val)
developerb8925a22015-11-16 14:38:40 +080052{
53 uint32_t ret;
54
55 ret = mtcmos_non_cpu_ctrl(0, val);
56 if (ret)
57 return MTK_SIP_E_INVALID_PARAM;
58 else
59 return MTK_SIP_E_SUCCESS;
60}
61
developer73b982f2016-05-11 18:04:09 +080062static uint64_t mt_sip_pwr_mtcmos_support(void)
developerb8925a22015-11-16 14:38:40 +080063{
64 return MTK_SIP_E_SUCCESS;
65}
developer73b982f2016-05-11 18:04:09 +080066
67uint64_t mediatek_plat_sip_handler(uint32_t smc_fid,
68 uint64_t x1,
69 uint64_t x2,
70 uint64_t x3,
71 uint64_t x4,
72 void *cookie,
73 void *handle,
74 uint64_t flags)
75{
76 uint64_t ret;
77
78 switch (smc_fid) {
79 case MTK_SIP_PWR_ON_MTCMOS:
80 ret = mt_sip_pwr_on_mtcmos((uint32_t)x1);
81 SMC_RET1(handle, ret);
82
83 case MTK_SIP_PWR_OFF_MTCMOS:
84 ret = mt_sip_pwr_off_mtcmos((uint32_t)x1);
85 SMC_RET1(handle, ret);
86
87 case MTK_SIP_PWR_MTCMOS_SUPPORT:
88 ret = mt_sip_pwr_mtcmos_support();
89 SMC_RET1(handle, ret);
90
developereee29802016-05-11 18:45:20 +080091 case MTK_SIP_SET_HDCP_KEY_EX:
92 ret = crypt_set_hdcp_key_ex(x1, x2, x3);
93 SMC_RET1(handle, ret);
94
95 case MTK_SIP_SET_HDCP_KEY_NUM:
96 ret = crypt_set_hdcp_key_num((uint32_t)x1);
97 SMC_RET1(handle, ret);
98
99 case MTK_SIP_CLR_HDCP_KEY:
100 ret = crypt_clear_hdcp_key();
101 SMC_RET1(handle, ret);
102
developer73b982f2016-05-11 18:04:09 +0800103 default:
104 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
105 break;
106 }
107
108 SMC_RET1(handle, SMC_UNK);
109}