Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 1 | /* |
Varun Wadekar | fadd538 | 2019-01-11 14:48:41 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <arch.h> |
| 9 | #include <asm_macros.S> |
Varun Wadekar | fadd538 | 2019-01-11 14:48:41 -0800 | [diff] [blame] | 10 | #include <common/bl_common.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 11 | #include <memctrl_v2.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <plat/common/common_def.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 13 | #include <tegra_def.h> |
| 14 | |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 15 | #define TEGRA186_MC_CTX_SIZE 0x93 |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 16 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 17 | .globl tegra186_cpu_reset_handler |
| 18 | |
| 19 | /* CPU reset handler routine */ |
Julius Werner | b4c75e9 | 2017-08-01 15:16:36 -0700 | [diff] [blame] | 20 | func tegra186_cpu_reset_handler _align=4 |
Varun Wadekar | 2a7d87e | 2017-11-10 10:26:57 -0800 | [diff] [blame] | 21 | /* prepare to relocate to TZSRAM */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 22 | mov x0, #BL31_BASE |
| 23 | adr x1, __tegra186_cpu_reset_handler_end |
| 24 | adr x2, __tegra186_cpu_reset_handler_data |
| 25 | ldr x2, [x2, #8] |
| 26 | |
| 27 | /* memcpy16 */ |
| 28 | m_loop16: |
| 29 | cmp x2, #16 |
| 30 | b.lt m_loop1 |
| 31 | ldp x3, x4, [x1], #16 |
| 32 | stp x3, x4, [x0], #16 |
| 33 | sub x2, x2, #16 |
| 34 | b m_loop16 |
| 35 | /* copy byte per byte */ |
| 36 | m_loop1: |
| 37 | cbz x2, boot_cpu |
| 38 | ldrb w3, [x1], #1 |
| 39 | strb w3, [x0], #1 |
| 40 | subs x2, x2, #1 |
| 41 | b.ne m_loop1 |
| 42 | |
| 43 | boot_cpu: |
| 44 | adr x0, __tegra186_cpu_reset_handler_data |
| 45 | ldr x0, [x0] |
| 46 | br x0 |
| 47 | endfunc tegra186_cpu_reset_handler |
| 48 | |
| 49 | /* |
| 50 | * Tegra186 reset data (offset 0x0 - 0x430) |
| 51 | * |
| 52 | * 0x000: secure world's entrypoint |
| 53 | * 0x008: BL31 size (RO + RW) |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 54 | * 0x00C: MC context start |
| 55 | * 0x42C: MC context end |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 56 | */ |
| 57 | |
| 58 | .align 4 |
| 59 | .type __tegra186_cpu_reset_handler_data, %object |
| 60 | .globl __tegra186_cpu_reset_handler_data |
| 61 | __tegra186_cpu_reset_handler_data: |
| 62 | .quad tegra_secure_entrypoint |
| 63 | .quad __BL31_END__ - BL31_BASE |
Varun Wadekar | fa88767 | 2017-11-08 14:45:08 -0800 | [diff] [blame] | 64 | |
Varun Wadekar | 2a7d87e | 2017-11-10 10:26:57 -0800 | [diff] [blame] | 65 | .globl __tegra186_system_suspend_state |
| 66 | __tegra186_system_suspend_state: |
| 67 | .quad 0 |
| 68 | |
Varun Wadekar | fa88767 | 2017-11-08 14:45:08 -0800 | [diff] [blame] | 69 | .align 4 |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 70 | .globl __tegra186_mc_context |
| 71 | __tegra186_mc_context: |
| 72 | .rept TEGRA186_MC_CTX_SIZE |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 73 | .quad 0 |
| 74 | .endr |
| 75 | .size __tegra186_cpu_reset_handler_data, \ |
| 76 | . - __tegra186_cpu_reset_handler_data |
| 77 | |
| 78 | .align 4 |
| 79 | .globl __tegra186_cpu_reset_handler_end |
| 80 | __tegra186_cpu_reset_handler_end: |
Varun Wadekar | 8304fc8 | 2017-10-25 11:52:07 -0700 | [diff] [blame] | 81 | |
| 82 | .globl tegra186_get_cpu_reset_handler_size |
| 83 | .globl tegra186_get_cpu_reset_handler_base |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 84 | .globl tegra186_get_mc_ctx_offset |
Varun Wadekar | 8304fc8 | 2017-10-25 11:52:07 -0700 | [diff] [blame] | 85 | |
| 86 | /* return size of the CPU reset handler */ |
| 87 | func tegra186_get_cpu_reset_handler_size |
| 88 | adr x0, __tegra186_cpu_reset_handler_end |
| 89 | adr x1, tegra186_cpu_reset_handler |
| 90 | sub x0, x0, x1 |
| 91 | ret |
| 92 | endfunc tegra186_get_cpu_reset_handler_size |
| 93 | |
| 94 | /* return the start address of the CPU reset handler */ |
| 95 | func tegra186_get_cpu_reset_handler_base |
| 96 | adr x0, tegra186_cpu_reset_handler |
| 97 | ret |
| 98 | endfunc tegra186_get_cpu_reset_handler_base |
Varun Wadekar | fa88767 | 2017-11-08 14:45:08 -0800 | [diff] [blame] | 99 | |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 100 | /* return the size of the MC context */ |
| 101 | func tegra186_get_mc_ctx_offset |
| 102 | adr x0, __tegra186_mc_context |
Varun Wadekar | fa88767 | 2017-11-08 14:45:08 -0800 | [diff] [blame] | 103 | adr x1, tegra186_cpu_reset_handler |
| 104 | sub x0, x0, x1 |
| 105 | ret |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 106 | endfunc tegra186_get_mc_ctx_offset |