Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / f3c8f3289d3d5c3eea01ea1c930ad1f8d16466fb / . / bl2 / aarch64 / bl2_entrypoint.S
blob: 6bc779a05592377f19344f7c60b12a60b5e965a9 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Dan Handleye83b0ca2014-01-14 18:17:09 +0000[diff] [blame]2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <bl_common.h>
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]32#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]33#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]34
35
36 .globl bl2_entrypoint
37
38
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]39
Andrew Thoelke38bde412014-03-18 13:46:55 +0000[diff] [blame]40func bl2_entrypoint
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]41 /*---------------------------------------------
42 * Store the extents of the tzram available to
43 * BL2 for future use. Use the opcode param to
44 * allow implement other functions if needed.
45 * ---------------------------------------------
46 */
47 mov x20, x0
48 mov x21, x1
49 mov x22, x2
50
51 /* ---------------------------------------------
52 * This is BL2 which is expected to be executed
53 * only by the primary cpu (at least for now).
54 * So, make sure no secondary has lost its way.
55 * ---------------------------------------------
56 */
57 bl read_mpidr
58 mov x19, x0
59 bl platform_is_primary_cpu
60 cbz x0, _panic
61
Sandrine Bailleuxc10bd2c2013-11-12 16:41:16 +0000[diff] [blame]62 /* ---------------------------------------------
63 * Set the exception vector to something sane.
64 * ---------------------------------------------
65 */
66 adr x0, early_exceptions
67 msr vbar_el1, x0
68
69 /* ---------------------------------------------
70 * Enable the instruction cache.
71 * ---------------------------------------------
72 */
73 mrs x0, sctlr_el1
74 orr x0, x0, #SCTLR_I_BIT
75 msr sctlr_el1, x0
76
77 isb
78
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]79 /* ---------------------------------------------
Sandrine Bailleux34edaed2013-12-02 15:45:07 +0000[diff] [blame]80 * Check the opcodes out of paranoia.
81 * ---------------------------------------------
82 */
83 mov x0, #RUN_IMAGE
84 cmp x0, x20
85 b.ne _panic
86
87 /* ---------------------------------------------
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000[diff] [blame]88 * Zero out NOBITS sections. There are 2 of them:
89 * - the .bss section;
90 * - the coherent memory section.
91 * ---------------------------------------------
92 */
93 ldr x0, =__BSS_START__
94 ldr x1, =__BSS_SIZE__
95 bl zeromem16
96
97 ldr x0, =__COHERENT_RAM_START__
98 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
99 bl zeromem16
100
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]101 /* --------------------------------------------
102 * Give ourselves a small coherent stack to
103 * ease the pain of initializing the MMU
104 * --------------------------------------------
105 */
106 mov x0, x19
107 bl platform_set_coherent_stack
108
109 /* ---------------------------------------------
110 * Perform early platform setup & platform
111 * specific early arch. setup e.g. mmu setup
112 * ---------------------------------------------
113 */
114 mov x0, x21
115 mov x1, x22
116 bl bl2_early_platform_setup
117 bl bl2_plat_arch_setup
118
119 /* ---------------------------------------------
120 * Give ourselves a stack allocated in Normal
121 * -IS-WBWA memory
122 * ---------------------------------------------
123 */
124 mov x0, x19
125 bl platform_set_stack
126
127 /* ---------------------------------------------
128 * Jump to main function.
129 * ---------------------------------------------
130 */
131 bl bl2_main
132_panic:
133 b _panic