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Yatharth Kochar5d361212016-06-28 17:07:09 +01001/*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Yatharth Kochar5d361212016-06-28 17:07:09 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kochar5d361212016-06-28 17:07:09 +01005 */
6
Yatharth Kochar5d361212016-06-28 17:07:09 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <arch_helpers.h>
Yatharth Kochar5d361212016-06-28 17:07:09 +010010#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/debug.h>
12#include <lib/el3_runtime/context_mgmt.h>
13#include <plat/common/platform.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000014#include <smccc_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015
Etienne Carriereba7c3d52017-06-07 16:41:50 +020016#include "../bl1_private.h"
Yatharth Kochar5d361212016-06-28 17:07:09 +010017
18/*
19 * Following arrays will be used for context management.
20 * There are 2 instances, for the Secure and Non-Secure contexts.
21 */
22static cpu_context_t bl1_cpu_context[2];
23static smc_ctx_t bl1_smc_context[2];
24
25/* Following contains the next cpu context pointer. */
26static void *bl1_next_cpu_context_ptr;
27
28/* Following contains the next smc context pointer. */
29static void *bl1_next_smc_context_ptr;
30
31/* Following functions are used for SMC context handling */
Etienne Carrierebfe12d32017-06-07 16:45:42 +020032void *smc_get_ctx(unsigned int security_state)
Yatharth Kochar5d361212016-06-28 17:07:09 +010033{
34 assert(sec_state_is_valid(security_state));
35 return &bl1_smc_context[security_state];
36}
37
Etienne Carrierebfe12d32017-06-07 16:45:42 +020038void smc_set_next_ctx(unsigned int security_state)
Yatharth Kochar5d361212016-06-28 17:07:09 +010039{
40 assert(sec_state_is_valid(security_state));
41 bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
42}
43
44void *smc_get_next_ctx(void)
45{
46 return bl1_next_smc_context_ptr;
47}
48
49/* Following functions are used for CPU context handling */
50void *cm_get_context(uint32_t security_state)
51{
52 assert(sec_state_is_valid(security_state));
53 return &bl1_cpu_context[security_state];
54}
55
56void cm_set_next_context(void *cpu_context)
57{
58 assert(cpu_context);
59 bl1_next_cpu_context_ptr = cpu_context;
60}
61
62void *cm_get_next_context(void)
63{
64 return bl1_next_cpu_context_ptr;
65}
66
67/*******************************************************************************
68 * Following function copies GP regs r0-r4, lr and spsr,
69 * from the CPU context to the SMC context structures.
70 ******************************************************************************/
71static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
72 smc_ctx_t *next_smc_ctx)
73{
74 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
75 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
76 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
77 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
78 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
79 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
Soby Mathewf3e3a432017-03-30 14:42:54 +010080 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
Yatharth Kochar5d361212016-06-28 17:07:09 +010081}
82
83/*******************************************************************************
84 * Following function flushes the SMC & CPU context pointer and its data.
85 ******************************************************************************/
86static void flush_smc_and_cpu_ctx(void)
87{
88 flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
89 sizeof(bl1_next_smc_context_ptr));
90 flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
91 sizeof(smc_ctx_t));
92
93 flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
94 sizeof(bl1_next_cpu_context_ptr));
95 flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
96 sizeof(cpu_context_t));
97}
98
99/*******************************************************************************
100 * This function prepares the context for Secure/Normal world images.
101 * Normal world images are transitioned to HYP(if supported) else SVC.
102 ******************************************************************************/
103void bl1_prepare_next_image(unsigned int image_id)
104{
105 unsigned int security_state;
106 image_desc_t *image_desc;
107 entry_point_info_t *next_bl_ep;
108
109 /* Get the image descriptor. */
110 image_desc = bl1_plat_get_image_desc(image_id);
111 assert(image_desc);
112
113 /* Get the entry point info. */
114 next_bl_ep = &image_desc->ep_info;
115
116 /* Get the image security state. */
117 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
118
119 /* Prepare the SPSR for the next BL image. */
120 if (security_state == SECURE) {
121 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
122 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
123 } else {
124 /* Use HYP mode if supported else use SVC. */
Yatharth Kochar64abad22016-09-23 10:48:29 +0100125 if (GET_VIRT_EXT(read_id_pfr1())) {
Yatharth Kochar5d361212016-06-28 17:07:09 +0100126 next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
127 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
128 } else {
129 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
130 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
131 }
132 }
133
134 /* Allow platform to make change */
135 bl1_plat_set_ep_info(image_id, next_bl_ep);
136
137 /* Prepare the cpu context for the next BL image. */
138 cm_init_my_context(next_bl_ep);
139 cm_prepare_el3_exit(security_state);
140 cm_set_next_context(cm_get_context(security_state));
141
142 /* Prepare the smc context for the next BL image. */
143 smc_set_next_ctx(security_state);
144 copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
145 smc_get_next_ctx());
146
147 /*
Soby Mathewf3e3a432017-03-30 14:42:54 +0100148 * If the next image is non-secure, then we need to program the banked
149 * non secure sctlr. This is not required when the next image is secure
150 * because in AArch32, we expect the secure world to have the same
151 * SCTLR settings.
152 */
153 if (security_state == NON_SECURE) {
154 cpu_context_t *ctx = cm_get_context(security_state);
155 u_register_t ns_sctlr;
156
157 /* Temporarily set the NS bit to access NS SCTLR */
158 write_scr(read_scr() | SCR_NS_BIT);
159 isb();
160
161 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
162 write_sctlr(ns_sctlr);
163 isb();
164
165 write_scr(read_scr() & ~SCR_NS_BIT);
166 isb();
167 }
168
169 /*
Yatharth Kochar5d361212016-06-28 17:07:09 +0100170 * Flush the SMC & CPU context and the (next)pointers,
171 * to access them after caches are disabled.
172 */
173 flush_smc_and_cpu_ctx();
174
175 /* Indicate that image is in execution state. */
176 image_desc->state = IMAGE_STATE_EXECUTED;
177
178 print_entry_point_info(next_bl_ep);
179}