| Loh Tien Hock | 59400a4 | 2019-02-04 16:17:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #define AXI_AP (1<<0) |
| 8 | #define FPGA2SOC (1<<16) |
| 9 | #define MPU (1<<24) |
| 10 | #define S10_NOC_PER_SCR_NAND 0xffd21000 |
| 11 | #define S10_NOC_PER_SCR_NAND_DATA 0xffd21004 |
| 12 | #define S10_NOC_PER_SCR_USB0 0xffd2100c |
| 13 | #define S10_NOC_PER_SCR_USB1 0xffd21010 |
| 14 | #define S10_NOC_PER_SCR_SPI_M0 0xffd2101c |
| 15 | #define S10_NOC_PER_SCR_SPI_M1 0xffd21020 |
| 16 | #define S10_NOC_PER_SCR_SPI_S0 0xffd21024 |
| 17 | #define S10_NOC_PER_SCR_SPI_S1 0xffd21028 |
| 18 | #define S10_NOC_PER_SCR_EMAC0 0xffd2102c |
| 19 | #define S10_NOC_PER_SCR_EMAC1 0xffd21030 |
| 20 | #define S10_NOC_PER_SCR_EMAC2 0xffd21034 |
| 21 | #define S10_NOC_PER_SCR_SDMMC 0xffd21040 |
| 22 | #define S10_NOC_PER_SCR_GPIO0 0xffd21044 |
| 23 | #define S10_NOC_PER_SCR_GPIO1 0xffd21048 |
| 24 | #define S10_NOC_PER_SCR_I2C0 0xffd21050 |
| 25 | #define S10_NOC_PER_SCR_I2C1 0xffd21058 |
| 26 | #define S10_NOC_PER_SCR_I2C2 0xffd2105c |
| 27 | #define S10_NOC_PER_SCR_I2C3 0xffd21060 |
| 28 | #define S10_NOC_PER_SCR_SP_TIMER0 0xffd21064 |
| 29 | #define S10_NOC_PER_SCR_SP_TIMER1 0xffd21068 |
| 30 | #define S10_NOC_PER_SCR_UART0 0xffd2106c |
| 31 | #define S10_NOC_PER_SCR_UART1 0xffd21070 |
| 32 | |
| 33 | |
| 34 | #define S10_NOC_SYS_SCR_DMA_ECC 0xffd21108 |
| 35 | #define S10_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c |
| 36 | #define S10_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110 |
| 37 | #define S10_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114 |
| 38 | #define S10_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118 |
| 39 | #define S10_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c |
| 40 | #define S10_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120 |
| 41 | #define S10_NOC_SYS_SCR_NAND_ECC 0xffd2112c |
| 42 | #define S10_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130 |
| 43 | #define S10_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134 |
| 44 | #define S10_NOC_SYS_SCR_OCRAM_ECC 0xffd21138 |
| 45 | #define S10_NOC_SYS_SCR_SDMMC_ECC 0xffd21140 |
| 46 | #define S10_NOC_SYS_SCR_USB0_ECC 0xffd21144 |
| 47 | #define S10_NOC_SYS_SCR_USB1_ECC 0xffd21148 |
| 48 | #define S10_NOC_SYS_SCR_CLK_MGR 0xffd2114c |
| 49 | #define S10_NOC_SYS_SCR_IO_MGR 0xffd21154 |
| 50 | #define S10_NOC_SYS_SCR_RST_MGR 0xffd21158 |
| 51 | #define S10_NOC_SYS_SCR_SYS_MGR 0xffd2115c |
| 52 | #define S10_NOC_SYS_SCR_OSC0_TIMER 0xffd21160 |
| 53 | #define S10_NOC_SYS_SCR_OSC1_TIMER 0xffd21164 |
| 54 | #define S10_NOC_SYS_SCR_WATCHDOG0 0xffd21168 |
| 55 | #define S10_NOC_SYS_SCR_WATCHDOG1 0xffd2116c |
| 56 | #define S10_NOC_SYS_SCR_WATCHDOG2 0xffd21170 |
| 57 | #define S10_NOC_SYS_SCR_WATCHDOG3 0xffd21174 |
| 58 | #define S10_NOC_SYS_SCR_DAP 0xffd21178 |
| 59 | #define S10_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190 |
| 60 | #define S10_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194 |
| 61 | |
| 62 | #define S10_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688 |
| 63 | #define S10_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688 |