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Louis Mayencourtf57f1082019-05-14 11:00:45 +01001/*
2 * Copyright (c) 2019, ARM Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CORTEX_HERCULES_H
8#define CORTEX_HERCULES_H
9
10#include <lib/utils_def.h>
11
12#define CORTEX_HERCULES_MIDR U(0x410FD410)
13
14/*******************************************************************************
15 * CPU Extended Control register specific definitions.
16 ******************************************************************************/
17#define CORTEX_HERCULES_CPUECTLR_EL1 S3_0_C15_C1_4
18
19/*******************************************************************************
20 * CPU Power Control register specific definitions
21 ******************************************************************************/
22#define CORTEX_HERCULES_CPUPWRCTLR_EL1 S3_0_C15_C2_7
23#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
24
Balint Dobszaydb2ec852019-07-15 11:46:20 +020025/*******************************************************************************
26 * CPU Auxiliary Control register specific definitions.
27 ******************************************************************************/
28#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
29
30/*******************************************************************************
31 * CPU Activity Monitor Unit register specific definitions.
32 ******************************************************************************/
33#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
34#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
35#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
36#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
37
38#define CORTEX_HERCULES_AMU_GROUP0_MASK U(0xF)
39#define CORTEX_HERCULES_AMU_GROUP1_MASK U(0x7)
40
Louis Mayencourtf57f1082019-05-14 11:00:45 +010041#endif /* CORTEX_HERCULES_H */