Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 1 | /* |
Sieu Mun Tang | dbcc2cf | 2022-03-07 12:13:04 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SOCFPGA_RESETMANAGER_H |
| 8 | #define SOCFPGA_RESETMANAGER_H |
| 9 | |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 10 | #include "socfpga_plat_def.h" |
| 11 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 12 | #define SOCFPGA_BRIDGE_ENABLE BIT(0) |
| 13 | #define SOCFPGA_BRIDGE_HAS_MASK BIT(1) |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 14 | |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 15 | #define SOC2FPGA_MASK (1<<0) |
| 16 | #define LWHPS2FPGA_MASK (1<<1) |
| 17 | #define FPGA2SOC_MASK (1<<2) |
| 18 | #define F2SDRAM0_MASK (1<<3) |
| 19 | #define F2SDRAM1_MASK (1<<4) |
| 20 | #define F2SDRAM2_MASK (1<<5) |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 21 | |
| 22 | /* Register Mapping */ |
| 23 | |
| 24 | #define SOCFPGA_RSTMGR_STAT 0x000 |
| 25 | #define SOCFPGA_RSTMGR_HDSKEN 0x010 |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 26 | #define SOCFPGA_RSTMGR_HDSKREQ 0x014 |
| 27 | #define SOCFPGA_RSTMGR_HDSKACK 0x018 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 28 | #define SOCFPGA_RSTMGR_MPUMODRST 0x020 |
| 29 | #define SOCFPGA_RSTMGR_PER0MODRST 0x024 |
| 30 | #define SOCFPGA_RSTMGR_PER1MODRST 0x028 |
| 31 | #define SOCFPGA_RSTMGR_BRGMODRST 0x02c |
| 32 | #define SOCFPGA_RSTMGR_COLDMODRST 0x034 |
| 33 | #define SOCFPGA_RSTMGR_HDSKTIMEOUT 0x064 |
| 34 | |
| 35 | /* Field Mapping */ |
| 36 | |
| 37 | #define RSTMGR_PER0MODRST_EMAC0 0x00000001 |
| 38 | #define RSTMGR_PER0MODRST_EMAC1 0x00000002 |
| 39 | #define RSTMGR_PER0MODRST_EMAC2 0x00000004 |
| 40 | #define RSTMGR_PER0MODRST_USB0 0x00000008 |
| 41 | #define RSTMGR_PER0MODRST_USB1 0x00000010 |
| 42 | #define RSTMGR_PER0MODRST_NAND 0x00000020 |
| 43 | #define RSTMGR_PER0MODRST_SDMMC 0x00000080 |
| 44 | #define RSTMGR_PER0MODRST_EMAC0OCP 0x00000100 |
| 45 | #define RSTMGR_PER0MODRST_EMAC1OCP 0x00000200 |
| 46 | #define RSTMGR_PER0MODRST_EMAC2OCP 0x00000400 |
| 47 | #define RSTMGR_PER0MODRST_USB0OCP 0x00000800 |
| 48 | #define RSTMGR_PER0MODRST_USB1OCP 0x00001000 |
| 49 | #define RSTMGR_PER0MODRST_NANDOCP 0x00002000 |
| 50 | #define RSTMGR_PER0MODRST_SDMMCOCP 0x00008000 |
| 51 | #define RSTMGR_PER0MODRST_DMA 0x00010000 |
| 52 | #define RSTMGR_PER0MODRST_SPIM0 0x00020000 |
| 53 | #define RSTMGR_PER0MODRST_SPIM1 0x00040000 |
| 54 | #define RSTMGR_PER0MODRST_SPIS0 0x00080000 |
| 55 | #define RSTMGR_PER0MODRST_SPIS1 0x00100000 |
| 56 | #define RSTMGR_PER0MODRST_DMAOCP 0x00200000 |
| 57 | #define RSTMGR_PER0MODRST_EMACPTP 0x00400000 |
| 58 | #define RSTMGR_PER0MODRST_DMAIF0 0x01000000 |
| 59 | #define RSTMGR_PER0MODRST_DMAIF1 0x02000000 |
| 60 | #define RSTMGR_PER0MODRST_DMAIF2 0x04000000 |
| 61 | #define RSTMGR_PER0MODRST_DMAIF3 0x08000000 |
| 62 | #define RSTMGR_PER0MODRST_DMAIF4 0x10000000 |
| 63 | #define RSTMGR_PER0MODRST_DMAIF5 0x20000000 |
| 64 | #define RSTMGR_PER0MODRST_DMAIF6 0x40000000 |
| 65 | #define RSTMGR_PER0MODRST_DMAIF7 0x80000000 |
| 66 | |
| 67 | #define RSTMGR_PER1MODRST_WATCHDOG0 0x00000001 |
| 68 | #define RSTMGR_PER1MODRST_WATCHDOG1 0x00000002 |
| 69 | #define RSTMGR_PER1MODRST_WATCHDOG2 0x00000004 |
| 70 | #define RSTMGR_PER1MODRST_WATCHDOG3 0x00000008 |
| 71 | #define RSTMGR_PER1MODRST_L4SYSTIMER0 0x00000010 |
| 72 | #define RSTMGR_PER1MODRST_L4SYSTIMER1 0x00000020 |
| 73 | #define RSTMGR_PER1MODRST_SPTIMER0 0x00000040 |
| 74 | #define RSTMGR_PER1MODRST_SPTIMER1 0x00000080 |
| 75 | #define RSTMGR_PER1MODRST_I2C0 0x00000100 |
| 76 | #define RSTMGR_PER1MODRST_I2C1 0x00000200 |
| 77 | #define RSTMGR_PER1MODRST_I2C2 0x00000400 |
| 78 | #define RSTMGR_PER1MODRST_I2C3 0x00000800 |
| 79 | #define RSTMGR_PER1MODRST_I2C4 0x00001000 |
| 80 | #define RSTMGR_PER1MODRST_UART0 0x00010000 |
| 81 | #define RSTMGR_PER1MODRST_UART1 0x00020000 |
| 82 | #define RSTMGR_PER1MODRST_GPIO0 0x01000000 |
| 83 | #define RSTMGR_PER1MODRST_GPIO1 0x02000000 |
| 84 | |
| 85 | #define RSTMGR_HDSKEN_FPGAHSEN 0x00000004 |
| 86 | #define RSTMGR_HDSKEN_ETRSTALLEN 0x00000008 |
| 87 | #define RSTMGR_HDSKEN_L2FLUSHEN 0x00000100 |
| 88 | #define RSTMGR_HDSKEN_L3NOC_DBG 0x00010000 |
| 89 | #define RSTMGR_HDSKEN_DEBUG_L3NOC 0x00020000 |
| 90 | #define RSTMGR_HDSKEN_SDRSELFREFEN 0x00000001 |
| 91 | |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 92 | #define RSTMGR_HDSKEQ_FPGAHSREQ 0x4 |
| 93 | |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 94 | #define RSTMGR_BRGMODRST_SOC2FPGA 0x1 |
| 95 | #define RSTMGR_BRGMODRST_LWHPS2FPGA 0x2 |
| 96 | #define RSTMGR_BRGMODRST_FPGA2SOC 0x4 |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 97 | #define RSTMGR_BRGMODRST_F2SSDRAM0 0x8 |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 98 | #define RSTMGR_BRGMODRST_F2SSDRAM1 0x10 |
| 99 | #define RSTMGR_BRGMODRST_F2SSDRAM2 0x20 |
| 100 | #define RSTMGR_BRGMODRST_MPFE 0x40 |
| 101 | #define RSTMGR_BRGMODRST_DDRSCH 0x40 |
| 102 | |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 103 | #define RSTMGR_HDSKREQ_FPGAHSREQ (BIT(2)) |
| 104 | #define RSTMGR_HDSKACK_FPGAHSACK_MASK (BIT(2)) |
| 105 | |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 106 | /* Definitions */ |
| 107 | |
| 108 | #define RSTMGR_L2_MODRST 0x0100 |
| 109 | #define RSTMGR_HDSKEN_SET 0x010D |
| 110 | |
| 111 | /* Macros */ |
| 112 | |
| 113 | #define SOCFPGA_RSTMGR(_reg) (SOCFPGA_RSTMGR_REG_BASE \ |
Sieu Mun Tang | 044ed48 | 2022-05-11 10:45:19 +0800 | [diff] [blame] | 114 | + (SOCFPGA_RSTMGR_##_reg)) |
Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 115 | #define RSTMGR_FIELD(_reg, _field) (RSTMGR_##_reg##MODRST_##_field) |
| 116 | |
| 117 | /* Function Declarations */ |
| 118 | |
| 119 | void deassert_peripheral_reset(void); |
| 120 | void config_hps_hs_before_warm_reset(void); |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 121 | |
Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame] | 122 | int socfpga_bridges_enable(uint32_t mask); |
| 123 | int socfpga_bridges_disable(uint32_t mask); |
Hadi Asyrafi | 5fae68f | 2019-10-22 14:23:57 +0800 | [diff] [blame] | 124 | |
| 125 | #endif /* SOCFPGA_RESETMANAGER_H */ |