Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 1 | /* |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 2 | * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a77.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 24 | /* -------------------------------------------------- |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 25 | * Errata Workaround for Cortex A77 Errata #1508412. |
| 26 | * This applies only to revision <= r1p0 of Cortex A77. |
| 27 | * Inputs: |
| 28 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 29 | * Shall clobber: x0-x17 |
| 30 | * -------------------------------------------------- |
| 31 | */ |
| 32 | func errata_a77_1508412_wa |
| 33 | /* |
| 34 | * Compare x0 against revision r1p0 |
| 35 | */ |
| 36 | mov x17, x30 |
| 37 | bl check_errata_1508412 |
| 38 | cbz x0, 3f |
| 39 | /* |
| 40 | * Compare x0 against revision r0p0 |
| 41 | */ |
| 42 | bl check_errata_1508412_0 |
| 43 | cbz x0, 1f |
| 44 | ldr x0, =0x0 |
| 45 | msr CORTEX_A77_CPUPSELR_EL3, x0 |
| 46 | ldr x0, =0x00E8400000 |
| 47 | msr CORTEX_A77_CPUPOR_EL3, x0 |
| 48 | ldr x0, =0x00FFE00000 |
| 49 | msr CORTEX_A77_CPUPMR_EL3, x0 |
| 50 | ldr x0, =0x4004003FF |
| 51 | msr CORTEX_A77_CPUPCR_EL3, x0 |
| 52 | ldr x0, =0x1 |
| 53 | msr CORTEX_A77_CPUPSELR_EL3, x0 |
| 54 | ldr x0, =0x00E8C00040 |
| 55 | msr CORTEX_A77_CPUPOR_EL3, x0 |
| 56 | ldr x0, =0x00FFE00040 |
| 57 | msr CORTEX_A77_CPUPMR_EL3, x0 |
| 58 | b 2f |
| 59 | 1: |
| 60 | ldr x0, =0x0 |
| 61 | msr CORTEX_A77_CPUPSELR_EL3, x0 |
| 62 | ldr x0, =0x00E8400000 |
| 63 | msr CORTEX_A77_CPUPOR_EL3, x0 |
| 64 | ldr x0, =0x00FF600000 |
| 65 | msr CORTEX_A77_CPUPMR_EL3, x0 |
| 66 | ldr x0, =0x00E8E00080 |
| 67 | msr CORTEX_A77_CPUPOR2_EL3, x0 |
| 68 | ldr x0, =0x00FFE000C0 |
| 69 | msr CORTEX_A77_CPUPMR2_EL3, x0 |
| 70 | 2: |
| 71 | ldr x0, =0x04004003FF |
| 72 | msr CORTEX_A77_CPUPCR_EL3, x0 |
| 73 | isb |
| 74 | 3: |
| 75 | ret x17 |
| 76 | endfunc errata_a77_1508412_wa |
| 77 | |
| 78 | func check_errata_1508412 |
| 79 | mov x1, #0x10 |
| 80 | b cpu_rev_var_ls |
| 81 | endfunc check_errata_1508412 |
| 82 | |
| 83 | func check_errata_1508412_0 |
| 84 | mov x1, #0x0 |
| 85 | b cpu_rev_var_ls |
| 86 | endfunc check_errata_1508412_0 |
| 87 | |
| 88 | /* -------------------------------------------------- |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 89 | * Errata Workaround for Cortex A77 Errata #1925769. |
| 90 | * This applies to revision <= r1p1 of Cortex A77. |
| 91 | * Inputs: |
| 92 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 93 | * Shall clobber: x0-x17 |
| 94 | * -------------------------------------------------- |
| 95 | */ |
| 96 | func errata_a77_1925769_wa |
| 97 | /* Compare x0 against revision <= r1p1 */ |
| 98 | mov x17, x30 |
| 99 | bl check_errata_1925769 |
| 100 | cbz x0, 1f |
| 101 | |
| 102 | /* Set bit 8 in ECTLR_EL1 */ |
| 103 | mrs x1, CORTEX_A77_CPUECTLR_EL1 |
| 104 | orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 |
| 105 | msr CORTEX_A77_CPUECTLR_EL1, x1 |
| 106 | isb |
| 107 | 1: |
| 108 | ret x17 |
| 109 | endfunc errata_a77_1925769_wa |
| 110 | |
| 111 | func check_errata_1925769 |
| 112 | /* Applies to everything <= r1p1 */ |
| 113 | mov x1, #0x11 |
| 114 | b cpu_rev_var_ls |
| 115 | endfunc check_errata_1925769 |
| 116 | |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 117 | /* -------------------------------------------------- |
| 118 | * Errata Workaround for Cortex A77 Errata #1946167. |
| 119 | * This applies to revision <= r1p1 of Cortex A77. |
| 120 | * Inputs: |
| 121 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 122 | * Shall clobber: x0-x17 |
| 123 | * -------------------------------------------------- |
| 124 | */ |
| 125 | func errata_a77_1946167_wa |
| 126 | /* Compare x0 against revision <= r1p1 */ |
| 127 | mov x17, x30 |
| 128 | bl check_errata_1946167 |
| 129 | cbz x0, 1f |
| 130 | |
| 131 | ldr x0,=0x4 |
| 132 | msr CORTEX_A77_CPUPSELR_EL3,x0 |
| 133 | ldr x0,=0x10E3900002 |
| 134 | msr CORTEX_A77_CPUPOR_EL3,x0 |
| 135 | ldr x0,=0x10FFF00083 |
| 136 | msr CORTEX_A77_CPUPMR_EL3,x0 |
| 137 | ldr x0,=0x2001003FF |
| 138 | msr CORTEX_A77_CPUPCR_EL3,x0 |
| 139 | |
| 140 | ldr x0,=0x5 |
| 141 | msr CORTEX_A77_CPUPSELR_EL3,x0 |
| 142 | ldr x0,=0x10E3800082 |
| 143 | msr CORTEX_A77_CPUPOR_EL3,x0 |
| 144 | ldr x0,=0x10FFF00083 |
| 145 | msr CORTEX_A77_CPUPMR_EL3,x0 |
| 146 | ldr x0,=0x2001003FF |
| 147 | msr CORTEX_A77_CPUPCR_EL3,x0 |
| 148 | |
| 149 | ldr x0,=0x6 |
| 150 | msr CORTEX_A77_CPUPSELR_EL3,x0 |
| 151 | ldr x0,=0x10E3800200 |
| 152 | msr CORTEX_A77_CPUPOR_EL3,x0 |
| 153 | ldr x0,=0x10FFF003E0 |
| 154 | msr CORTEX_A77_CPUPMR_EL3,x0 |
| 155 | ldr x0,=0x2001003FF |
| 156 | msr CORTEX_A77_CPUPCR_EL3,x0 |
| 157 | |
| 158 | isb |
| 159 | 1: |
| 160 | ret x17 |
| 161 | endfunc errata_a77_1946167_wa |
| 162 | |
| 163 | func check_errata_1946167 |
| 164 | /* Applies to everything <= r1p1 */ |
| 165 | mov x1, #0x11 |
| 166 | b cpu_rev_var_ls |
| 167 | endfunc check_errata_1946167 |
| 168 | |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 169 | /* ------------------------------------------------- |
| 170 | * The CPU Ops reset function for Cortex-A77. |
| 171 | * Shall clobber: x0-x19 |
| 172 | * ------------------------------------------------- |
| 173 | */ |
| 174 | func cortex_a77_reset_func |
| 175 | mov x19, x30 |
| 176 | bl cpu_get_rev_var |
| 177 | mov x18, x0 |
| 178 | |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 179 | #if ERRATA_A77_1508412 |
| 180 | mov x0, x18 |
| 181 | bl errata_a77_1508412_wa |
| 182 | #endif |
| 183 | |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 184 | #if ERRATA_A77_1925769 |
| 185 | mov x0, x18 |
| 186 | bl errata_a77_1925769_wa |
| 187 | #endif |
| 188 | |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 189 | #if ERRATA_A77_1946167 |
| 190 | mov x0, x18 |
| 191 | bl errata_a77_1946167_wa |
| 192 | #endif |
| 193 | |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 194 | ret x19 |
| 195 | endfunc cortex_a77_reset_func |
| 196 | |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 197 | /* --------------------------------------------- |
| 198 | * HW will do the cache maintenance while powering down |
| 199 | * --------------------------------------------- |
| 200 | */ |
| 201 | func cortex_a77_core_pwr_dwn |
| 202 | /* --------------------------------------------- |
| 203 | * Enable CPU power down bit in power control register |
| 204 | * --------------------------------------------- |
| 205 | */ |
| 206 | mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 |
| 207 | orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 208 | msr CORTEX_A77_CPUPWRCTLR_EL1, x0 |
| 209 | isb |
| 210 | ret |
| 211 | endfunc cortex_a77_core_pwr_dwn |
| 212 | |
| 213 | #if REPORT_ERRATA |
| 214 | /* |
| 215 | * Errata printing function for Cortex-A77. Must follow AAPCS. |
| 216 | */ |
| 217 | func cortex_a77_errata_report |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 218 | stp x8, x30, [sp, #-16]! |
| 219 | |
| 220 | bl cpu_get_rev_var |
| 221 | mov x8, x0 |
| 222 | |
| 223 | /* |
| 224 | * Report all errata. The revision-variant information is passed to |
| 225 | * checking functions of each errata. |
| 226 | */ |
laurenw-arm | 99ad976 | 2020-07-14 14:18:34 -0500 | [diff] [blame] | 227 | report_errata ERRATA_A77_1508412, cortex_a77, 1508412 |
johpow01 | a2fa12c | 2020-09-10 13:39:26 -0500 | [diff] [blame] | 228 | report_errata ERRATA_A77_1925769, cortex_a77, 1925769 |
laurenw-arm | f5dbbef | 2021-03-23 13:09:35 -0500 | [diff] [blame] | 229 | report_errata ERRATA_A77_1946167, cortex_a77, 1946167 |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 230 | |
| 231 | ldp x8, x30, [sp], #16 |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 232 | ret |
| 233 | endfunc cortex_a77_errata_report |
| 234 | #endif |
| 235 | |
| 236 | |
| 237 | /* --------------------------------------------- |
| 238 | * This function provides Cortex-A77 specific |
| 239 | * register information for crash reporting. |
| 240 | * It needs to return with x6 pointing to |
| 241 | * a list of register names in ascii and |
| 242 | * x8 - x15 having values of registers to be |
| 243 | * reported. |
| 244 | * --------------------------------------------- |
| 245 | */ |
| 246 | .section .rodata.cortex_a77_regs, "aS" |
| 247 | cortex_a77_regs: /* The ascii list of register names to be reported */ |
| 248 | .asciz "cpuectlr_el1", "" |
| 249 | |
| 250 | func cortex_a77_cpu_reg_dump |
| 251 | adr x6, cortex_a77_regs |
| 252 | mrs x8, CORTEX_A77_CPUECTLR_EL1 |
| 253 | ret |
| 254 | endfunc cortex_a77_cpu_reg_dump |
| 255 | |
| 256 | declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ |
johpow01 | 68aedc7 | 2020-06-03 15:23:31 -0500 | [diff] [blame] | 257 | cortex_a77_reset_func, \ |
Balint Dobszay | cc94264 | 2019-07-03 13:02:56 +0200 | [diff] [blame] | 258 | cortex_a77_core_pwr_dwn |