Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 1 | /* |
Roberto Vargas | 0571270 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 7 | #ifndef CPU_DATA_H |
| 8 | #define CPU_DATA_H |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 9 | |
Jeenu Viswambharan | 10a6727 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 10 | #include <ehf.h> |
Etienne Carriere | 97ad6ce | 2017-09-01 10:22:20 +0200 | [diff] [blame] | 11 | #include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */ |
| 12 | |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 13 | #ifdef AARCH32 |
| 14 | |
| 15 | #if CRASH_REPORTING |
| 16 | #error "Crash reporting is not supported in AArch32" |
| 17 | #endif |
| 18 | #define CPU_DATA_CPU_OPS_PTR 0x0 |
Etienne Carriere | 97ad6ce | 2017-09-01 10:22:20 +0200 | [diff] [blame] | 19 | #define CPU_DATA_CRASH_BUF_OFFSET 0x4 |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 20 | |
| 21 | #else /* AARCH32 */ |
| 22 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 23 | /* Offsets for the cpu_data structure */ |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 24 | #define CPU_DATA_CRASH_BUF_OFFSET 0x18 |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 25 | /* need enough space in crash buffer to save 8 registers */ |
| 26 | #define CPU_DATA_CRASH_BUF_SIZE 64 |
| 27 | #define CPU_DATA_CPU_OPS_PTR 0x10 |
| 28 | |
| 29 | #endif /* AARCH32 */ |
| 30 | |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 31 | #if CRASH_REPORTING |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 32 | #define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \ |
| 33 | CPU_DATA_CRASH_BUF_SIZE) |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 34 | #else |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 35 | #define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 36 | #endif |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 37 | |
Etienne Carriere | 97ad6ce | 2017-09-01 10:22:20 +0200 | [diff] [blame] | 38 | /* cpu_data size is the data size rounded up to the platform cache line size */ |
| 39 | #define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \ |
| 40 | CACHE_WRITEBACK_GRANULE - 1) / \ |
| 41 | CACHE_WRITEBACK_GRANULE) * \ |
| 42 | CACHE_WRITEBACK_GRANULE) |
| 43 | |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 44 | #if ENABLE_RUNTIME_INSTRUMENTATION |
| 45 | /* Temporary space to store PMF timestamps from assembly code */ |
| 46 | #define CPU_DATA_PMF_TS_COUNT 1 |
| 47 | #define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END |
| 48 | #define CPU_DATA_PMF_TS0_IDX 0 |
| 49 | #endif |
| 50 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 51 | #ifndef __ASSEMBLY__ |
| 52 | |
| 53 | #include <arch_helpers.h> |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 54 | #include <cassert.h> |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 55 | #include <platform_def.h> |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 56 | #include <psci.h> |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 57 | #include <stdint.h> |
| 58 | |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 59 | /* Offsets for the cpu_data structure */ |
| 60 | #define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\ |
| 61 | (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info) |
| 62 | |
| 63 | #if PLAT_PCPU_DATA_SIZE |
| 64 | #define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\ |
| 65 | (cpu_data_t, platform_cpu_data) |
| 66 | #endif |
| 67 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 68 | /******************************************************************************* |
| 69 | * Function & variable prototypes |
| 70 | ******************************************************************************/ |
| 71 | |
| 72 | /******************************************************************************* |
| 73 | * Cache of frequently used per-cpu data: |
Andrew Thoelke | c02dbd6 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 74 | * Pointers to non-secure and secure security state contexts |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 75 | * Address of the crash stack |
| 76 | * It is aligned to the cache line boundary to allow efficient concurrent |
| 77 | * manipulation of these pointers on different cpus |
| 78 | * |
| 79 | * TODO: Add other commonly used variables to this (tf_issues#90) |
| 80 | * |
| 81 | * The data structure and the _cpu_data accessors should not be used directly |
| 82 | * by components that have per-cpu members. The member access macros should be |
| 83 | * used for this. |
| 84 | ******************************************************************************/ |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 85 | typedef struct cpu_data { |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 86 | #ifndef AARCH32 |
Andrew Thoelke | c02dbd6 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 87 | void *cpu_context[2]; |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 88 | #endif |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 89 | uintptr_t cpu_ops_ptr; |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 90 | #if CRASH_REPORTING |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 91 | u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 92 | #endif |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 93 | #if ENABLE_RUNTIME_INSTRUMENTATION |
| 94 | uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT]; |
| 95 | #endif |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 96 | struct psci_cpu_data psci_svc_cpu_data; |
| 97 | #if PLAT_PCPU_DATA_SIZE |
| 98 | uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; |
| 99 | #endif |
Jeenu Viswambharan | 10a6727 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 100 | #if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING |
| 101 | pe_exc_data_t ehf_data; |
| 102 | #endif |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 103 | } __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; |
| 104 | |
Roberto Vargas | 0571270 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 105 | extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; |
| 106 | |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 107 | #if CRASH_REPORTING |
| 108 | /* verify assembler offsets match data structures */ |
| 109 | CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof |
| 110 | (cpu_data_t, crash_buf), |
| 111 | assert_cpu_data_crash_stack_offset_mismatch); |
| 112 | #endif |
| 113 | |
Etienne Carriere | 97ad6ce | 2017-09-01 10:22:20 +0200 | [diff] [blame] | 114 | CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t), |
| 115 | assert_cpu_data_size_mismatch); |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 116 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 117 | CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof |
| 118 | (cpu_data_t, cpu_ops_ptr), |
| 119 | assert_cpu_data_cpu_ops_ptr_offset_mismatch); |
| 120 | |
dp-arm | 3cac786 | 2016-09-19 11:18:44 +0100 | [diff] [blame] | 121 | #if ENABLE_RUNTIME_INSTRUMENTATION |
| 122 | CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof |
| 123 | (cpu_data_t, cpu_data_pmf_ts[0]), |
| 124 | assert_cpu_data_pmf_ts0_offset_mismatch); |
| 125 | #endif |
| 126 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 127 | struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 128 | |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 129 | #ifndef AARCH32 |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 130 | /* Return the cpu_data structure for the current CPU. */ |
| 131 | static inline struct cpu_data *_cpu_data(void) |
| 132 | { |
| 133 | return (cpu_data_t *)read_tpidr_el3(); |
| 134 | } |
Soby Mathew | 748be1d | 2016-05-05 14:10:46 +0100 | [diff] [blame] | 135 | #else |
| 136 | struct cpu_data *_cpu_data(void); |
| 137 | #endif |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 138 | |
| 139 | /************************************************************************** |
| 140 | * APIs for initialising and accessing per-cpu data |
| 141 | *************************************************************************/ |
| 142 | |
| 143 | void init_cpu_data_ptr(void); |
Vikram Kanigiri | 9b38fc8 | 2015-01-29 18:27:38 +0000 | [diff] [blame] | 144 | void init_cpu_ops(void); |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 145 | |
| 146 | #define get_cpu_data(_m) _cpu_data()->_m |
| 147 | #define set_cpu_data(_m, _v) _cpu_data()->_m = _v |
| 148 | #define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m |
| 149 | #define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v |
Joel Hutton | 43a4d57 | 2017-10-20 10:31:14 +0100 | [diff] [blame] | 150 | /* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */ |
Soby Mathew | 24ab34f | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 151 | #define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \ |
Joel Hutton | 43a4d57 | 2017-10-20 10:31:14 +0100 | [diff] [blame] | 152 | &(_cpu_data()->_m), \ |
| 153 | sizeof(((cpu_data_t *)0)->_m)) |
Soby Mathew | 24ab34f | 2016-05-03 17:11:42 +0100 | [diff] [blame] | 154 | #define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \ |
Joel Hutton | 43a4d57 | 2017-10-20 10:31:14 +0100 | [diff] [blame] | 155 | &(_cpu_data()->_m), \ |
| 156 | sizeof(((cpu_data_t *)0)->_m)) |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 157 | #define flush_cpu_data_by_index(_ix, _m) \ |
Soby Mathew | a0fedc4 | 2016-06-16 14:52:04 +0100 | [diff] [blame] | 158 | flush_dcache_range((uintptr_t) \ |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 159 | &(_cpu_data_by_index(_ix)->_m), \ |
Joel Hutton | 43a4d57 | 2017-10-20 10:31:14 +0100 | [diff] [blame] | 160 | sizeof(((cpu_data_t *)0)->_m)) |
Achin Gupta | e4b9fa4 | 2014-07-25 14:47:05 +0100 | [diff] [blame] | 161 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 162 | |
| 163 | #endif /* __ASSEMBLY__ */ |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 164 | #endif /* CPU_DATA_H */ |