Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <arch_helpers.h> |
| 9 | #include <assert.h> |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 10 | #include <cassert.h> |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 11 | #include <sys/types.h> |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 12 | #include <utils_def.h> |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 13 | #include <xlat_tables_v2.h> |
| 14 | #include "../xlat_tables_private.h" |
| 15 | |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 16 | uint32_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; |
| 17 | |
Antonio Nino Diaz | 4413ad5 | 2018-06-11 13:40:32 +0100 | [diff] [blame] | 18 | /* |
| 19 | * Returns 1 if the provided granule size is supported, 0 otherwise. |
| 20 | */ |
| 21 | int xlat_arch_is_granule_size_supported(size_t size) |
| 22 | { |
| 23 | u_register_t id_aa64mmfr0_el1 = read_id_aa64mmfr0_el1(); |
| 24 | |
| 25 | if (size == (4U * 1024U)) { |
| 26 | return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN4_SHIFT) & |
| 27 | ID_AA64MMFR0_EL1_TGRAN4_MASK) == |
| 28 | ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED; |
| 29 | } else if (size == (16U * 1024U)) { |
| 30 | return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN16_SHIFT) & |
| 31 | ID_AA64MMFR0_EL1_TGRAN16_MASK) == |
| 32 | ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED; |
| 33 | } else if (size == (64U * 1024U)) { |
| 34 | return ((id_aa64mmfr0_el1 >> ID_AA64MMFR0_EL1_TGRAN64_SHIFT) & |
| 35 | ID_AA64MMFR0_EL1_TGRAN64_MASK) == |
| 36 | ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED; |
| 37 | } |
| 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | size_t xlat_arch_get_max_supported_granule_size(void) |
| 43 | { |
| 44 | if (xlat_arch_is_granule_size_supported(64U * 1024U)) { |
| 45 | return 64U * 1024U; |
| 46 | } else if (xlat_arch_is_granule_size_supported(16U * 1024U)) { |
| 47 | return 16U * 1024U; |
| 48 | } else { |
| 49 | assert(xlat_arch_is_granule_size_supported(4U * 1024U)); |
| 50 | return 4U * 1024U; |
| 51 | } |
| 52 | } |
| 53 | |
Antonio Nino Diaz | bafc753 | 2017-10-25 11:53:25 +0100 | [diff] [blame] | 54 | unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 55 | { |
| 56 | /* Physical address can't exceed 48 bits */ |
| 57 | assert((max_addr & ADDR_MASK_48_TO_63) == 0); |
| 58 | |
| 59 | /* 48 bits address */ |
| 60 | if (max_addr & ADDR_MASK_44_TO_47) |
| 61 | return TCR_PS_BITS_256TB; |
| 62 | |
| 63 | /* 44 bits address */ |
| 64 | if (max_addr & ADDR_MASK_42_TO_43) |
| 65 | return TCR_PS_BITS_16TB; |
| 66 | |
| 67 | /* 42 bits address */ |
| 68 | if (max_addr & ADDR_MASK_40_TO_41) |
| 69 | return TCR_PS_BITS_4TB; |
| 70 | |
| 71 | /* 40 bits address */ |
| 72 | if (max_addr & ADDR_MASK_36_TO_39) |
| 73 | return TCR_PS_BITS_1TB; |
| 74 | |
| 75 | /* 36 bits address */ |
| 76 | if (max_addr & ADDR_MASK_32_TO_35) |
| 77 | return TCR_PS_BITS_64GB; |
| 78 | |
| 79 | return TCR_PS_BITS_4GB; |
| 80 | } |
| 81 | |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 82 | #if ENABLE_ASSERTIONS |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 83 | /* |
| 84 | * Physical Address ranges supported in the AArch64 Memory Model. Value 0b110 is |
| 85 | * supported in ARMv8.2 onwards. |
| 86 | */ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 87 | static const unsigned int pa_range_bits_arr[] = { |
| 88 | PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, |
Antonio Nino Diaz | b9ae5db | 2018-05-02 11:23:56 +0100 | [diff] [blame] | 89 | PARANGE_0101, PARANGE_0110 |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 90 | }; |
| 91 | |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 92 | unsigned long long xlat_arch_get_max_supported_pa(void) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 93 | { |
| 94 | u_register_t pa_range = read_id_aa64mmfr0_el1() & |
| 95 | ID_AA64MMFR0_EL1_PARANGE_MASK; |
| 96 | |
| 97 | /* All other values are reserved */ |
| 98 | assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); |
| 99 | |
David Cunado | c150312 | 2018-02-16 21:12:58 +0000 | [diff] [blame] | 100 | return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL; |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 101 | } |
Antonio Nino Diaz | 3759e3f | 2017-03-22 15:48:51 +0000 | [diff] [blame] | 102 | #endif /* ENABLE_ASSERTIONS*/ |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 103 | |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 104 | int is_mmu_enabled_ctx(const xlat_ctx_t *ctx) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 105 | { |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 106 | if (ctx->xlat_regime == EL1_EL0_REGIME) { |
| 107 | assert(xlat_arch_current_el() >= 1); |
| 108 | return (read_sctlr_el1() & SCTLR_M_BIT) != 0; |
| 109 | } else { |
| 110 | assert(ctx->xlat_regime == EL3_REGIME); |
| 111 | assert(xlat_arch_current_el() >= 3); |
| 112 | return (read_sctlr_el3() & SCTLR_M_BIT) != 0; |
| 113 | } |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 114 | } |
| 115 | |
Antonio Nino Diaz | dcf9d92 | 2017-10-04 16:52:15 +0100 | [diff] [blame] | 116 | |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 117 | void xlat_arch_tlbi_va(uintptr_t va) |
| 118 | { |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 119 | #if IMAGE_EL == 1 |
| 120 | assert(IS_IN_EL(1)); |
| 121 | xlat_arch_tlbi_va_regime(va, EL1_EL0_REGIME); |
| 122 | #elif IMAGE_EL == 3 |
| 123 | assert(IS_IN_EL(3)); |
| 124 | xlat_arch_tlbi_va_regime(va, EL3_REGIME); |
| 125 | #endif |
| 126 | } |
| 127 | |
Antonio Nino Diaz | f1b84f6 | 2018-07-03 11:58:49 +0100 | [diff] [blame] | 128 | void xlat_arch_tlbi_va_regime(uintptr_t va, int xlat_regime) |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 129 | { |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 130 | /* |
| 131 | * Ensure the translation table write has drained into memory before |
| 132 | * invalidating the TLB entry. |
| 133 | */ |
| 134 | dsbishst(); |
| 135 | |
Douglas Raillard | 2d54579 | 2017-09-25 15:23:22 +0100 | [diff] [blame] | 136 | /* |
| 137 | * This function only supports invalidation of TLB entries for the EL3 |
| 138 | * and EL1&0 translation regimes. |
| 139 | * |
| 140 | * Also, it is architecturally UNDEFINED to invalidate TLBs of a higher |
| 141 | * exception level (see section D4.9.2 of the ARM ARM rev B.a). |
| 142 | */ |
| 143 | if (xlat_regime == EL1_EL0_REGIME) { |
| 144 | assert(xlat_arch_current_el() >= 1); |
| 145 | tlbivaae1is(TLBI_ADDR(va)); |
| 146 | } else { |
| 147 | assert(xlat_regime == EL3_REGIME); |
| 148 | assert(xlat_arch_current_el() >= 3); |
| 149 | tlbivae3is(TLBI_ADDR(va)); |
| 150 | } |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | void xlat_arch_tlbi_va_sync(void) |
| 154 | { |
| 155 | /* |
| 156 | * A TLB maintenance instruction can complete at any time after |
| 157 | * it is issued, but is only guaranteed to be complete after the |
| 158 | * execution of DSB by the PE that executed the TLB maintenance |
| 159 | * instruction. After the TLB invalidate instruction is |
| 160 | * complete, no new memory accesses using the invalidated TLB |
| 161 | * entries will be observed by any observer of the system |
| 162 | * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph |
| 163 | * "Ordering and completion of TLB maintenance instructions". |
| 164 | */ |
| 165 | dsbish(); |
| 166 | |
| 167 | /* |
| 168 | * The effects of a completed TLB maintenance instruction are |
| 169 | * only guaranteed to be visible on the PE that executed the |
| 170 | * instruction after the execution of an ISB instruction by the |
| 171 | * PE that executed the TLB maintenance instruction. |
| 172 | */ |
| 173 | isb(); |
| 174 | } |
| 175 | |
Antonio Nino Diaz | efabaa9 | 2017-04-27 13:30:22 +0100 | [diff] [blame] | 176 | int xlat_arch_current_el(void) |
| 177 | { |
| 178 | int el = GET_EL(read_CurrentEl()); |
| 179 | |
| 180 | assert(el > 0); |
| 181 | |
| 182 | return el; |
| 183 | } |
| 184 | |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 185 | void setup_mmu_cfg(unsigned int flags, |
| 186 | const uint64_t *base_table, |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 187 | unsigned long long max_pa, |
| 188 | uintptr_t max_va) |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 189 | { |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 190 | uint64_t mair, ttbr, tcr; |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 191 | uintptr_t virtual_addr_space_size; |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 192 | |
| 193 | /* Set attributes in the right indices of the MAIR. */ |
| 194 | mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); |
| 195 | mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX); |
| 196 | mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); |
| 197 | |
| 198 | ttbr = (uint64_t) base_table; |
| 199 | |
| 200 | /* |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 201 | * Limit the input address ranges and memory region sizes translated |
| 202 | * using TTBR0 to the given virtual address space size. |
| 203 | */ |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 204 | assert(max_va < ((uint64_t) UINTPTR_MAX)); |
| 205 | |
| 206 | virtual_addr_space_size = max_va + 1; |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 207 | assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size)); |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 208 | |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 209 | /* |
Sandrine Bailleux | 12e8644 | 2017-07-19 10:11:13 +0100 | [diff] [blame] | 210 | * __builtin_ctzll(0) is undefined but here we are guaranteed that |
Sandrine Bailleux | 46c53a2 | 2017-07-11 15:11:10 +0100 | [diff] [blame] | 211 | * virtual_addr_space_size is in the range [1,UINTPTR_MAX]. |
| 212 | */ |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 213 | tcr = (uint64_t) 64 - __builtin_ctzll(virtual_addr_space_size); |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 214 | |
| 215 | /* |
| 216 | * Set the cacheability and shareability attributes for memory |
| 217 | * associated with translation table walks. |
| 218 | */ |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 219 | if ((flags & XLAT_TABLE_NC) != 0) { |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 220 | /* Inner & outer non-cacheable non-shareable. */ |
| 221 | tcr |= TCR_SH_NON_SHAREABLE | |
| 222 | TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC; |
| 223 | } else { |
| 224 | /* Inner & outer WBWA & shareable. */ |
| 225 | tcr |= TCR_SH_INNER_SHAREABLE | |
| 226 | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA; |
| 227 | } |
| 228 | |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 229 | /* |
| 230 | * It is safer to restrict the max physical address accessible by the |
| 231 | * hardware as much as possible. |
| 232 | */ |
Antonio Nino Diaz | bafc753 | 2017-10-25 11:53:25 +0100 | [diff] [blame] | 233 | unsigned long long tcr_ps_bits = tcr_physical_addr_size_bits(max_pa); |
Sandrine Bailleux | c5b6377 | 2017-05-31 13:31:48 +0100 | [diff] [blame] | 234 | |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 235 | #if IMAGE_EL == 1 |
| 236 | assert(IS_IN_EL(1)); |
Antonio Nino Diaz | c8274a8 | 2017-09-15 10:30:34 +0100 | [diff] [blame] | 237 | /* |
| 238 | * TCR_EL1.EPD1: Disable translation table walk for addresses that are |
| 239 | * translated using TTBR1_EL1. |
| 240 | */ |
| 241 | tcr |= TCR_EPD1_BIT | (tcr_ps_bits << TCR_EL1_IPS_SHIFT); |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 242 | #elif IMAGE_EL == 3 |
| 243 | assert(IS_IN_EL(3)); |
Sandrine Bailleux | 1423d05 | 2017-05-31 13:38:51 +0100 | [diff] [blame] | 244 | tcr |= TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT); |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 245 | #endif |
Jeenu Viswambharan | 58e8148 | 2018-04-27 15:06:57 +0100 | [diff] [blame] | 246 | |
| 247 | mmu_cfg_params[MMU_CFG_MAIR0] = (uint32_t) mair; |
| 248 | mmu_cfg_params[MMU_CFG_TCR] = (uint32_t) tcr; |
| 249 | |
| 250 | /* Set TTBR bits as well */ |
| 251 | if (ARM_ARCH_AT_LEAST(8, 2)) { |
| 252 | /* |
| 253 | * Enable CnP bit so as to share page tables with all PEs. This |
| 254 | * is mandatory for ARMv8.2 implementations. |
| 255 | */ |
| 256 | ttbr |= TTBR_CNP_BIT; |
| 257 | } |
| 258 | |
| 259 | mmu_cfg_params[MMU_CFG_TTBR0_LO] = (uint32_t) ttbr; |
| 260 | mmu_cfg_params[MMU_CFG_TTBR0_HI] = (uint32_t) (ttbr >> 32); |
Antonio Nino Diaz | 233c7c1 | 2017-03-08 14:40:23 +0000 | [diff] [blame] | 261 | } |