developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch_helpers.h> |
| 8 | #include <common/debug.h> |
| 9 | #include <lib/mmio.h> |
| 10 | #include <plat_debug.h> |
| 11 | #include <platform_def.h> |
developer | 083fa24 | 2019-08-21 20:50:20 +0800 | [diff] [blame] | 12 | #include <spm.h> |
developer | 1033ea1 | 2019-04-10 21:09:26 +0800 | [diff] [blame] | 13 | |
| 14 | void circular_buffer_setup(void) |
| 15 | { |
| 16 | /* Clear DBG_CONTROL.lastpc_disable to enable circular buffer */ |
| 17 | sync_writel(CA15M_DBG_CONTROL, |
| 18 | mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS)); |
| 19 | } |
| 20 | |
| 21 | void circular_buffer_unlock(void) |
| 22 | { |
| 23 | unsigned int i; |
| 24 | |
| 25 | /* Disable big vproc external off (set CPU_EXT_BUCK_ISO to 0x0) */ |
| 26 | sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1)); |
| 27 | |
| 28 | /* Release vproc apb mask (set 0x0C53_2008[1] to 0x0) */ |
| 29 | sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1)); |
| 30 | |
| 31 | for (i = 1; i <= 4; ++i) |
| 32 | sync_writel(MP1_CPUTOP_PWR_CON + i * 4, |
| 33 | (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4)); |
| 34 | |
| 35 | /* Set DFD.en */ |
| 36 | sync_writel(DFD_INTERNAL_CTL, 0x1); |
| 37 | } |
| 38 | |
| 39 | void circular_buffer_lock(void) |
| 40 | { |
| 41 | /* Clear DFD.en */ |
| 42 | sync_writel(DFD_INTERNAL_CTL, 0x0); |
| 43 | } |
| 44 | |
| 45 | void clear_all_on_mux(void) |
| 46 | { |
| 47 | sync_writel(MCU_ALL_PWR_ON_CTRL, |
| 48 | mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2)); |
| 49 | sync_writel(MCU_ALL_PWR_ON_CTRL, |
| 50 | mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1)); |
| 51 | } |
| 52 | |
| 53 | void l2c_parity_check_setup(void) |
| 54 | { |
| 55 | /* Enable DBG_CONTROL.l2parity_en */ |
| 56 | sync_writel(CA15M_DBG_CONTROL, |
| 57 | mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN); |
| 58 | } |