| Valentine Barshak | f218414 | 2018-10-30 02:06:17 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, Renesas Electronics Corporation |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <stdint.h> |
| 9 | #include <common/debug.h> |
| 10 | #include "qos_init_v3m.h" |
| 11 | |
| 12 | #define RCAR_QOS_VERSION "rev.0.01" |
| 13 | |
| 14 | #define RCAR_QOS_NONE (3U) |
| 15 | #define RCAR_QOS_TYPE_DEFAULT (0U) |
| 16 | |
| 17 | #define RCAR_DRAM_SPLIT_LINEAR (0U) |
| 18 | #define RCAR_DRAM_SPLIT_4CH (1U) |
| 19 | #define RCAR_DRAM_SPLIT_2CH (2U) |
| 20 | |
| 21 | #define DBSC_BASE (0xE6790000U) |
| 22 | #define DBSC_AXARB (DBSC_BASE + 0x0800U) |
| 23 | |
| 24 | #define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) |
| 25 | #define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) |
| 26 | #define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) |
| 27 | #define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) |
| 28 | #define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) |
| 29 | #define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) |
| 30 | #define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) |
| 31 | #define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) |
| 32 | #define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) |
| 33 | #define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) |
| 34 | #define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) |
| 35 | #define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) |
| 36 | #define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) |
| 37 | #define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) |
| 38 | #define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) |
| 39 | #define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) |
| 40 | #define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) |
| 41 | #define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) |
| 42 | #define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) |
| 43 | #define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) |
| 44 | #define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) |
| 45 | #define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) |
| 46 | #define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) |
| 47 | #define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) |
| 48 | #define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) |
| 49 | #define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) |
| 50 | #define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) |
| 51 | #define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) |
| 52 | #define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) |
| 53 | #define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) |
| 54 | #define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) |
| 55 | #define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) |
| 56 | #define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) |
| 57 | #define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) |
| 58 | #define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) |
| 59 | #define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) |
| 60 | #define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) |
| 61 | #define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) |
| 62 | #define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) |
| 63 | #define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) |
| 64 | #define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) |
| 65 | #define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) |
| 66 | #define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) |
| 67 | #define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) |
| 68 | #define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) |
| 69 | #define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) |
| 70 | #define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) |
| 71 | #define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) |
| 72 | #define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) |
| 73 | #define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) |
| 74 | #define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) |
| 75 | #define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) |
| 76 | #define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) |
| 77 | #define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) |
| 78 | #define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) |
| 79 | #define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) |
| 80 | #define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) |
| 81 | #define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) |
| 82 | #define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) |
| 83 | #define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) |
| 84 | #define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) |
| 85 | #define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) |
| 86 | #define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) |
| 87 | #define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) |
| 88 | #define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) |
| 89 | #define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) |
| 90 | #define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) |
| 91 | #define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) |
| 92 | #define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) |
| 93 | #define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) |
| 94 | #define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) |
| 95 | #define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) |
| 96 | #define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) |
| 97 | #define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) |
| 98 | #define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) |
| 99 | #define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) |
| 100 | #define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) |
| 101 | |
| 102 | #define AXI_BASE (0xE6784000U) |
| 103 | #define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) |
| 104 | #define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) |
| 105 | #define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) |
| 106 | #define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) |
| 107 | #define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) |
| 108 | #define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) |
| 109 | #define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) |
| 110 | #define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) |
| 111 | #define ADSPLCR0_SWP (0x0CU) |
| 112 | |
| 113 | #define MSTAT_BASE (0xE67E0000U) |
| 114 | #define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) |
| 115 | #define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) |
| 116 | #define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) |
| 117 | #define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) |
| 118 | #define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) |
| 119 | #define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) |
| 120 | #define MSTAT_STATQC (MSTAT_BASE + 0x8008U) |
| 121 | |
| 122 | #define RALLOC_BASE (0xE67F0000U) |
| 123 | #define RALLOC_RAS (RALLOC_BASE + 0x0000U) |
| 124 | #define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) |
| 125 | #define RALLOC_RAEN (RALLOC_BASE + 0x0018U) |
| 126 | #define RALLOC_REGGD (RALLOC_BASE + 0x0020U) |
| 127 | #define RALLOC_DANN (RALLOC_BASE + 0x0030U) |
| 128 | #define RALLOC_DANT (RALLOC_BASE + 0x0038U) |
| 129 | #define RALLOC_EC (RALLOC_BASE + 0x003CU) |
| 130 | #define RALLOC_EMS (RALLOC_BASE + 0x0040U) |
| 131 | #define RALLOC_INSFC (RALLOC_BASE + 0x0050U) |
| 132 | #define RALLOC_BERR (RALLOC_BASE + 0x0054U) |
| 133 | #define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) |
| 134 | |
| 135 | #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) |
| 136 | |
| 137 | |
| 138 | static inline void io_write_32(uintptr_t addr, uint32_t value) |
| 139 | { |
| 140 | *(volatile uint32_t*)addr = value; |
| 141 | } |
| 142 | |
| 143 | static inline void io_write_64(uintptr_t addr, uint64_t value) |
| 144 | { |
| 145 | *(volatile uint64_t*)addr = value; |
| 146 | } |
| 147 | |
| 148 | |
| 149 | typedef struct { |
| 150 | uintptr_t addr; |
| 151 | uint64_t value; |
| 152 | } mstat_slot_t; |
| 153 | |
| 154 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 155 | static const mstat_slot_t mstat_fix[] = { |
| 156 | {0x0000U, 0x000000000000FFFFU}, |
| 157 | {0x0008U, 0x000000000000FFFFU}, |
| 158 | {0x0010U, 0x000000000000FFFFU}, |
| 159 | {0x0018U, 0x000000000000FFFFU}, |
| 160 | {0x0020U, 0x001414090000FFFFU}, |
| 161 | {0x0028U, 0x000C00000000FFFFU}, |
| 162 | {0x0030U, 0x001008040000FFFFU}, |
| 163 | {0x0038U, 0x001004040000FFFFU}, |
| 164 | {0x0040U, 0x001004040000FFFFU}, |
| 165 | {0x0048U, 0x000000000000FFFFU}, |
| 166 | {0x0050U, 0x001004040000FFFFU}, |
| 167 | {0x0058U, 0x001004040000FFFFU}, |
| 168 | {0x0060U, 0x000000000000FFFFU}, |
| 169 | {0x0068U, 0x001404040000FFFFU}, |
| 170 | {0x0070U, 0x001008030000FFFFU}, |
| 171 | {0x0078U, 0x001004030000FFFFU}, |
| 172 | {0x0080U, 0x001004030000FFFFU}, |
| 173 | {0x0088U, 0x000000000000FFFFU}, |
| 174 | {0x0090U, 0x001004040000FFFFU}, |
| 175 | {0x0098U, 0x001004040000FFFFU}, |
| 176 | {0x00A0U, 0x000000000000FFFFU}, |
| 177 | {0x00A8U, 0x000000000000FFFFU}, |
| 178 | {0x00B0U, 0x000000000000FFFFU}, |
| 179 | {0x00B8U, 0x000000000000FFFFU}, |
| 180 | {0x00C0U, 0x000000000000FFFFU}, |
| 181 | {0x00C8U, 0x000000000000FFFFU}, |
| 182 | {0x00D0U, 0x000000000000FFFFU}, |
| 183 | {0x00D8U, 0x000000000000FFFFU}, |
| 184 | {0x00E0U, 0x001404020000FFFFU}, |
| 185 | {0x00E8U, 0x000000000000FFFFU}, |
| 186 | {0x00F0U, 0x000000000000FFFFU}, |
| 187 | {0x00F8U, 0x000000000000FFFFU}, |
| 188 | {0x0100U, 0x000000000000FFFFU}, |
| 189 | {0x0108U, 0x000C04020000FFFFU}, |
| 190 | {0x0110U, 0x000000000000FFFFU}, |
| 191 | {0x0118U, 0x001404020000FFFFU}, |
| 192 | {0x0120U, 0x000000000000FFFFU}, |
| 193 | {0x0128U, 0x000000000000FFFFU}, |
| 194 | {0x0130U, 0x000000000000FFFFU}, |
| 195 | {0x0138U, 0x000000000000FFFFU}, |
| 196 | {0x0140U, 0x000000000000FFFFU}, |
| 197 | {0x0148U, 0x000000000000FFFFU}, |
| 198 | }; |
| 199 | |
| 200 | static const mstat_slot_t mstat_be[] = { |
| 201 | {0x0000U, 0x00100020447FFC01U}, |
| 202 | {0x0008U, 0x00100020447FFC01U}, |
| 203 | {0x0010U, 0x00100040447FFC01U}, |
| 204 | {0x0018U, 0x00100040447FFC01U}, |
| 205 | {0x0020U, 0x0000000000000000U}, |
| 206 | {0x0028U, 0x0000000000000000U}, |
| 207 | {0x0030U, 0x0000000000000000U}, |
| 208 | {0x0038U, 0x0000000000000000U}, |
| 209 | {0x0040U, 0x0000000000000000U}, |
| 210 | {0x0048U, 0x0000000000000000U}, |
| 211 | {0x0050U, 0x0000000000000000U}, |
| 212 | {0x0058U, 0x0000000000000000U}, |
| 213 | {0x0060U, 0x0000000000000000U}, |
| 214 | {0x0068U, 0x0000000000000000U}, |
| 215 | {0x0070U, 0x0000000000000000U}, |
| 216 | {0x0078U, 0x0000000000000000U}, |
| 217 | {0x0080U, 0x0000000000000000U}, |
| 218 | {0x0088U, 0x0000000000000000U}, |
| 219 | {0x0090U, 0x0000000000000000U}, |
| 220 | {0x0098U, 0x0000000000000000U}, |
| 221 | {0x00A0U, 0x00100010447FFC01U}, |
| 222 | {0x00A8U, 0x00100010447FFC01U}, |
| 223 | {0x00B0U, 0x00100010447FFC01U}, |
| 224 | {0x00B8U, 0x00100010447FFC01U}, |
| 225 | {0x00C0U, 0x00100010447FFC01U}, |
| 226 | {0x00C8U, 0x00100010447FFC01U}, |
| 227 | {0x00D0U, 0x0000000000000000U}, |
| 228 | {0x00D8U, 0x00100010447FFC01U}, |
| 229 | {0x00E0U, 0x0000000000000000U}, |
| 230 | {0x00E8U, 0x00100010447FFC01U}, |
| 231 | {0x00F0U, 0x00100010447FFC01U}, |
| 232 | {0x00F8U, 0x00100010447FFC01U}, |
| 233 | {0x0100U, 0x00100010447FFC01U}, |
| 234 | {0x0108U, 0x0000000000000000U}, |
| 235 | {0x0110U, 0x00100010447FFC01U}, |
| 236 | {0x0118U, 0x0000000000000000U}, |
| 237 | {0x0120U, 0x00100010447FFC01U}, |
| 238 | {0x0128U, 0x00100010447FFC01U}, |
| 239 | {0x0130U, 0x00100010447FFC01U}, |
| 240 | {0x0138U, 0x00100010447FFC01U}, |
| 241 | {0x0140U, 0x00100020447FFC01U}, |
| 242 | {0x0148U, 0x00100020447FFC01U}, |
| 243 | }; |
| 244 | #endif |
| 245 | |
| 246 | static void dbsc_setting(void) |
| 247 | { |
| 248 | |
| 249 | /* BUFCAM settings */ |
| 250 | //DBSC_DBCAM0CNF0 not set |
| 251 | io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1 |
| 252 | io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 |
| 253 | //io_write_32(DBSC_DBCAM0CNF3, 0x00000007); //dbcam0cnf3 |
| 254 | io_write_32(DBSC_DBSCHCNT0, 0x080F003F); //dbschcnt0 |
| 255 | io_write_32(DBSC_DBSCHCNT1, 0x00001010); //dbschcnt0 |
| 256 | |
| 257 | io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 |
| 258 | io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 |
| 259 | io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1 |
| 260 | io_write_32(DBSC_SCFCTST0,0x180B1708); |
| 261 | io_write_32(DBSC_SCFCTST1,0x0808070C); |
| 262 | io_write_32(DBSC_SCFCTST2,0x012F1123); |
| 263 | |
| 264 | /* QoS Settings */ |
| 265 | io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000); |
| 266 | io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000); |
| 267 | io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000); |
| 268 | io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); |
| 269 | //DBSC_DBSCHQOS_1_0 not set |
| 270 | //DBSC_DBSCHQOS_1_1 not set |
| 271 | //DBSC_DBSCHQOS_1_2 not set |
| 272 | //DBSC_DBSCHQOS_1_3 not set |
| 273 | //DBSC_DBSCHQOS_2_0 not set |
| 274 | //DBSC_DBSCHQOS_2_1 not set |
| 275 | //DBSC_DBSCHQOS_2_2 not set |
| 276 | //DBSC_DBSCHQOS_2_3 not set |
| 277 | //DBSC_DBSCHQOS_3_0 not set |
| 278 | //DBSC_DBSCHQOS_3_1 not set |
| 279 | //DBSC_DBSCHQOS_3_2 not set |
| 280 | //DBSC_DBSCHQOS_3_3 not set |
| 281 | io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000); |
| 282 | io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF); |
| 283 | io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000); |
| 284 | io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000); |
| 285 | //DBSC_DBSCHQOS_5_0 not set |
| 286 | //DBSC_DBSCHQOS_5_1 not set |
| 287 | //DBSC_DBSCHQOS_5_2 not set |
| 288 | //DBSC_DBSCHQOS_5_3 not set |
| 289 | //DBSC_DBSCHQOS_6_0 not set |
| 290 | //DBSC_DBSCHQOS_6_1 not set |
| 291 | //DBSC_DBSCHQOS_6_2 not set |
| 292 | //DBSC_DBSCHQOS_6_3 not set |
| 293 | //DBSC_DBSCHQOS_7_0 not set |
| 294 | //DBSC_DBSCHQOS_7_1 not set |
| 295 | //DBSC_DBSCHQOS_7_2 not set |
| 296 | //DBSC_DBSCHQOS_7_3 not set |
| 297 | //DBSC_DBSCHQOS_8_0 not set |
| 298 | //DBSC_DBSCHQOS_8_1 not set |
| 299 | //DBSC_DBSCHQOS_8_2 not set |
| 300 | //DBSC_DBSCHQOS_8_3 not set |
| 301 | io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000); |
| 302 | io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF); |
| 303 | io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000); |
| 304 | io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000); |
| 305 | //DBSC_DBSCHQOS_10_0 not set |
| 306 | //DBSC_DBSCHQOS_10_1 not set |
| 307 | //DBSC_DBSCHQOS_10_2 not set |
| 308 | //DBSC_DBSCHQOS_10_3 not set |
| 309 | //DBSC_DBSCHQOS_11_0 not set |
| 310 | //DBSC_DBSCHQOS_11_1 not set |
| 311 | //DBSC_DBSCHQOS_11_2 not set |
| 312 | //DBSC_DBSCHQOS_11_3 not set |
| 313 | //DBSC_DBSCHQOS_12_0 not set |
| 314 | //DBSC_DBSCHQOS_12_1 not set |
| 315 | //DBSC_DBSCHQOS_12_2 not set |
| 316 | //DBSC_DBSCHQOS_12_3 not set |
| 317 | io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000); |
| 318 | io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF); |
| 319 | io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800); |
| 320 | io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000); |
| 321 | io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000); |
| 322 | io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF); |
| 323 | io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800); |
| 324 | io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000); |
| 325 | io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0); |
| 326 | io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF); |
| 327 | io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0); |
| 328 | io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0); |
| 329 | } |
| 330 | |
| 331 | void qos_init_v3m(void) |
| 332 | { |
| 333 | return; |
| 334 | |
| 335 | dbsc_setting(); |
| 336 | |
| 337 | #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) |
| 338 | #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT |
| 339 | NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); |
| 340 | #endif |
| 341 | |
| 342 | /* Resource Alloc setting */ |
| 343 | io_write_32(RALLOC_RAS, 0x00000020U); |
| 344 | io_write_32(RALLOC_FIXTH, 0x000F0005U); |
| 345 | io_write_32(RALLOC_REGGD, 0x00000004U); |
| 346 | io_write_64(RALLOC_DANN, 0x0202020104040200U); |
| 347 | io_write_32(RALLOC_DANT, 0x00201008U); |
| 348 | io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */ |
| 349 | io_write_64(RALLOC_EMS, 0x0000000000000000U); |
| 350 | io_write_32(RALLOC_INSFC, 0x63C20001U); |
| 351 | io_write_32(RALLOC_BERR, 0x00000000U); |
| 352 | |
| 353 | /* MSTAT setting */ |
| 354 | io_write_32(MSTAT_SL_INIT, 0x0305007DU); |
| 355 | io_write_32(MSTAT_REF_ARS, 0x00330000U); |
| 356 | |
| 357 | /* MSTAT SRAM setting */ |
| 358 | { |
| 359 | uint32_t i; |
| 360 | |
| 361 | for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { |
| 362 | io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, |
| 363 | mstat_fix[i].value); |
| 364 | io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, |
| 365 | mstat_fix[i].value); |
| 366 | } |
| 367 | for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { |
| 368 | io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, |
| 369 | mstat_be[i].value); |
| 370 | io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, |
| 371 | mstat_be[i].value); |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | /* AXI-IF arbitration setting */ |
| 376 | io_write_32(DBSC_AXARB, 0x18010000U); |
| 377 | |
| 378 | /* Resource Alloc start */ |
| 379 | io_write_32(RALLOC_RAEN, 0x00000001U); |
| 380 | |
| 381 | /* MSTAT start */ |
| 382 | io_write_32(MSTAT_STATQC, 0x00000001U); |
| 383 | |
| 384 | #else |
| 385 | NOTICE("BL2: QoS is None\n"); |
| 386 | #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ |
| 387 | } |