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git01.mediatek.com / filogic / atf / f154cbdd4833e48d9230bd16d9ee635e12da1e68 / . / plat / marvell / armada / a8k / common / plat_pm_trace.c
blob: e02a89386d70fc8f6a5d033f8a9ab488f0a0201f [file] [log] [blame]
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]1/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8#include <lib/mmio.h>
9#include <plat/common/platform.h>
10
Konstantin Porotchkin23099612020-10-12 18:13:07 +0300[diff] [blame]11#if MSS_SUPPORT
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]12#include <mss_mem.h>
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]13
14#ifdef PM_TRACE_ENABLE
Konstantin Porotchkin23099612020-10-12 18:13:07 +0300[diff] [blame]15#include <plat_pm_trace.h>
Konstantin Porotchkinf69ec582018-06-07 18:31:14 +0300[diff] [blame]16
17/* core trace APIs */
18core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
19 pm_core_0_trace,
20 pm_core_1_trace,
21 pm_core_2_trace,
22 pm_core_3_trace};
23
24/*****************************************************************************
25 * pm_core0_trace
26 * pm_core1_trace
27 * pm_core2_trace
28 * pm_core_3trace
29 *
30 * This functions set trace info into core cyclic trace queue in MSS SRAM
31 * memory space
32 *****************************************************************************
33 */
34void pm_core_0_trace(unsigned int trace)
35{
36 unsigned int current_position_core_0 =
37 mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE);
38 mmio_write_32((AP_MSS_ATF_CORE_0_INFO_BASE +
39 (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
40 mmio_read_32(AP_MSS_TIMER_BASE));
41 mmio_write_32((AP_MSS_ATF_CORE_0_INFO_TRACE +
42 (current_position_core_0 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
43 trace);
44 mmio_write_32(AP_MSS_ATF_CORE_0_CTRL_BASE,
45 ((current_position_core_0 + 1) &
46 AP_MSS_ATF_TRACE_SIZE_MASK));
47}
48
49void pm_core_1_trace(unsigned int trace)
50{
51 unsigned int current_position_core_1 =
52 mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE);
53 mmio_write_32((AP_MSS_ATF_CORE_1_INFO_BASE +
54 (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
55 mmio_read_32(AP_MSS_TIMER_BASE));
56 mmio_write_32((AP_MSS_ATF_CORE_1_INFO_TRACE +
57 (current_position_core_1 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
58 trace);
59 mmio_write_32(AP_MSS_ATF_CORE_1_CTRL_BASE,
60 ((current_position_core_1 + 1) &
61 AP_MSS_ATF_TRACE_SIZE_MASK));
62}
63
64void pm_core_2_trace(unsigned int trace)
65{
66 unsigned int current_position_core_2 =
67 mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE);
68 mmio_write_32((AP_MSS_ATF_CORE_2_INFO_BASE +
69 (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
70 mmio_read_32(AP_MSS_TIMER_BASE));
71 mmio_write_32((AP_MSS_ATF_CORE_2_INFO_TRACE +
72 (current_position_core_2 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
73 trace);
74 mmio_write_32(AP_MSS_ATF_CORE_2_CTRL_BASE,
75 ((current_position_core_2 + 1) &
76 AP_MSS_ATF_TRACE_SIZE_MASK));
77}
78
79void pm_core_3_trace(unsigned int trace)
80{
81 unsigned int current_position_core_3 =
82 mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE);
83 mmio_write_32((AP_MSS_ATF_CORE_3_INFO_BASE +
84 (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
85 mmio_read_32(AP_MSS_TIMER_BASE));
86 mmio_write_32((AP_MSS_ATF_CORE_3_INFO_TRACE +
87 (current_position_core_3 * AP_MSS_ATF_CORE_ENTRY_SIZE)),
88 trace);
89 mmio_write_32(AP_MSS_ATF_CORE_3_CTRL_BASE,
90 ((current_position_core_3 + 1) &
91 AP_MSS_ATF_TRACE_SIZE_MASK));
92}
93#endif /* PM_TRACE_ENABLE */
Konstantin Porotchkin23099612020-10-12 18:13:07 +0300[diff] [blame]94#endif /* MSS_SUPPORT */