blob: 923c4f1544d2427b19fd1a82470ab9e9f37a2db5 [file] [log] [blame]
Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +08002 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +08007#ifndef SOCFPGA_MBOX_H
8#define SOCFPGA_MBOX_H
Hadi Asyrafi616da772019-06-27 11:34:03 +08009
Ambroise Vincenta724e432019-07-23 11:10:27 +010010#include <lib/utils_def.h>
11
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080012
Hadi Asyrafi616da772019-06-27 11:34:03 +080013#define MBOX_OFFSET 0xffa30000
14
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080015#define MBOX_ATF_CLIENT_ID 0x1U
16#define MBOX_MAX_JOB_ID 0xFU
17#define MBOX_MAX_IND_JOB_ID (MBOX_MAX_JOB_ID - 1U)
18#define MBOX_JOB_ID MBOX_MAX_JOB_ID
Hadi Asyrafi616da772019-06-27 11:34:03 +080019
Hadi Asyrafi616da772019-06-27 11:34:03 +080020
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080021/* Mailbox Shared Memory Register Map */
Hadi Asyrafi616da772019-06-27 11:34:03 +080022#define MBOX_CIN 0x00
23#define MBOX_ROUT 0x04
24#define MBOX_URG 0x08
25#define MBOX_INT 0x0C
26#define MBOX_COUT 0x20
27#define MBOX_RIN 0x24
28#define MBOX_STATUS 0x2C
29#define MBOX_CMD_BUFFER 0x40
30#define MBOX_RESP_BUFFER 0xC0
31
Hadi Asyrafi616da772019-06-27 11:34:03 +080032/* Mailbox SDM doorbell */
33#define MBOX_DOORBELL_TO_SDM 0x400
34#define MBOX_DOORBELL_FROM_SDM 0x480
35
Hadi Asyrafi616da772019-06-27 11:34:03 +080036
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080037/* Mailbox commands */
Tien Hock, Loh527234a2019-10-30 14:54:25 +080038
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080039#define MBOX_CMD_NOOP 0x00
40#define MBOX_CMD_SYNC 0x01
41#define MBOX_CMD_RESTART 0x02
42#define MBOX_CMD_CANCEL 0x03
43#define MBOX_CMD_GET_IDCODE 0x10
44#define MBOX_CMD_REBOOT_HPS 0x47
Hadi Asyrafi616da772019-06-27 11:34:03 +080045
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080046/* Reconfiguration Commands */
47#define MBOX_CONFIG_STATUS 0x04
48#define MBOX_RECONFIG 0x06
49#define MBOX_RECONFIG_DATA 0x08
50#define MBOX_RECONFIG_STATUS 0x09
Hadi Asyrafi593c4c52019-12-17 19:22:17 +080051
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080052/* QSPI Commands */
53#define MBOX_CMD_QSPI_OPEN 0x32
54#define MBOX_CMD_QSPI_CLOSE 0x33
55#define MBOX_CMD_QSPI_SET_CS 0x34
56#define MBOX_CMD_QSPI_DIRECT 0x3B
57
58/* RSU Commands */
59#define MBOX_GET_SUBPARTITION_TABLE 0x5A
60#define MBOX_RSU_STATUS 0x5B
61#define MBOX_RSU_UPDATE 0x5C
62#define MBOX_HPS_STAGE_NOTIFY 0x5D
Hadi Asyrafi593c4c52019-12-17 19:22:17 +080063
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080064
65/* Mailbox Definitions */
66
67#define CMD_DIRECT 0
Abdul Halim, Muhammad Hadi Asyrafib45f15e2020-05-14 15:32:43 +080068#define CMD_INDIRECT 1
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080069#define CMD_CASUAL 0
70#define CMD_URGENT 1
71
72#define MBOX_RESP_BUFFER_SIZE 16
73#define MBOX_CMD_BUFFER_SIZE 32
Hadi Asyrafi593c4c52019-12-17 19:22:17 +080074
75/* Execution states for HPS_STAGE_NOTIFY */
76#define HPS_EXECUTION_STATE_FSBL 0
77#define HPS_EXECUTION_STATE_SSBL 1
78#define HPS_EXECUTION_STATE_OS 2
79
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080080/* Status Response */
81#define MBOX_RET_OK 0
82#define MBOX_RET_ERROR -1
Hadi Asyrafi616da772019-06-27 11:34:03 +080083#define MBOX_NO_RESPONSE -2
84#define MBOX_WRONG_ID -3
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080085#define MBOX_BUFFER_FULL -4
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080086#define MBOX_TIMEOUT -2047
Hadi Asyrafi616da772019-06-27 11:34:03 +080087
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080088/* Reconfig Status Response */
Hadi Asyrafi2b9198d2019-11-12 15:03:00 +080089#define RECONFIG_STATUS_STATE 0
90#define RECONFIG_STATUS_PIN_STATUS 2
91#define RECONFIG_STATUS_SOFTFUNC_STATUS 3
92#define PIN_STATUS_NSTATUS (U(1) << 31)
93#define SOFTFUNC_STATUS_SEU_ERROR (1 << 3)
94#define SOFTFUNC_STATUS_INIT_DONE (1 << 1)
95#define SOFTFUNC_STATUS_CONF_DONE (1 << 0)
96#define MBOX_CFGSTAT_STATE_IDLE 0x00000000
97#define MBOX_CFGSTAT_STATE_CONFIG 0x10000000
98#define MBOX_CFGSTAT_STATE_FAILACK 0x08000000
99#define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001
100#define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002
101#define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003
102#define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004
103#define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005
104#define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006
105#define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007
106#define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008
Hadi Asyrafi616da772019-06-27 11:34:03 +0800107
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800108
109/* Mailbox Macros */
110
111/* Mailbox interrupt flags and masks */
112#define MBOX_INT_FLAG_COE 0x1
113#define MBOX_INT_FLAG_RIE 0x2
114#define MBOX_INT_FLAG_UAE 0x100
115#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
116#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
117
118/* Mailbox response and status */
119#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff)
120#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
121#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
122#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
123#define MBOX_STATUS_UA_MASK (1<<8)
124
125/* Mailbox command and response */
126#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
127#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
128#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
Abdul Halim, Muhammad Hadi Asyrafib45f15e2020-05-14 15:32:43 +0800129#define MBOX_INDIRECT(val) ((val) << 11)
Chee Hong Ang5bc87bc2020-05-11 11:23:21 +0800130#define MBOX_CMD_MASK(header) ((header) & 0x7ff)
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800131
132/* RSU Macros */
133#define RSU_VERSION_ACMF BIT(8)
134#define RSU_VERSION_ACMF_MASK 0xff00
135
136
137/* Mailbox Function Definitions */
138
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +0800139void mailbox_set_int(uint32_t interrupt_input);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800140int mailbox_init(void);
141void mailbox_set_qspi_close(void);
142void mailbox_set_qspi_open(void);
143void mailbox_set_qspi_direct(void);
Abdul Halim, Muhammad Hadi Asyrafi118ab212020-10-15 15:27:18 +0800144
145int mailbox_send_cmd(uint32_t job_id, uint32_t cmd, uint32_t *args,
146 unsigned int len, uint32_t urgent, uint32_t *response,
147 unsigned int resp_len);
148int mailbox_send_cmd_async(uint32_t *job_id, uint32_t cmd, uint32_t *args,
149 unsigned int len, unsigned int indirect);
150int mailbox_read_response(uint32_t *job_id, uint32_t *response,
151 unsigned int resp_len);
152unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
153 unsigned int resp_len);
154
Hadi Asyrafi616da772019-06-27 11:34:03 +0800155void mailbox_reset_cold(void);
Tien Hock, Loh527234a2019-10-30 14:54:25 +0800156void mailbox_clear_response(void);
157
Abdul Halim, Muhammad Hadi Asyrafie59b9992020-02-11 20:17:05 +0800158int intel_mailbox_get_config_status(uint32_t cmd);
Hadi Asyrafi6aeb55d2019-12-24 14:43:22 +0800159int intel_mailbox_is_fpga_not_ready(void);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800160
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800161int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
162int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
Abdul Halim, Muhammad Hadi Asyrafid84bfef2020-02-25 16:28:10 +0800163int mailbox_rsu_update(uint32_t *flash_offset);
164int mailbox_hps_stage_notify(uint32_t execution_stage);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800165
Hadi Asyrafi6f8a2b22019-10-23 18:34:14 +0800166#endif /* SOCFPGA_MBOX_H */