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git01.mediatek.com / filogic / atf / f13d0e4a1af6d8f26651328404c0e043912318af / . / plat / arm / css / sgi / sgi-common.mk
blob: 4af579ee6acca80f12abe242b35ea9217a390fa8 [file] [log] [blame]
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]1#
Vijayenthiran Subramaniam063bb732021-11-25 21:54:30 +0530[diff] [blame]2# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chandni Cherukurid61a7052018-08-01 15:58:48 +0530[diff] [blame]7CSS_USE_SCMI_SDS_DRIVER := 1
8
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]9CSS_ENT_BASE := plat/arm/css/sgi
10
Sughosh Ganu3f7e79d2018-05-16 18:48:56 +0530[diff] [blame]11RAS_EXTENSION := 0
12
Sughosh Ganu3f7e79d2018-05-16 18:48:56 +0530[diff] [blame]13SDEI_SUPPORT := 0
14
15EL3_EXCEPTION_HANDLING := 0
16
17HANDLE_EA_EL3_FIRST := 0
18
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]19CSS_SGI_CHIP_COUNT := 1
20
Aditya Angadi06402222021-03-20 12:06:15 +0530[diff] [blame]21CSS_SGI_PLATFORM_VARIANT := 0
22
Vijayenthiran Subramaniam063bb732021-11-25 21:54:30 +0530[diff] [blame]23# Do not enable SVE
24ENABLE_SVE_FOR_NS := 0
25
Nishant Sharma469a6f62022-04-19 10:23:59 +0100[diff] [blame]26CTX_INCLUDE_FPREGS := 1
27
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]28INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c
29
30PLAT_INCLUDES += -I${CSS_ENT_BASE}/include
31
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]32# GIC-600 configuration
Andre Przywarae1cc1302020-03-25 15:50:38 +0000[diff] [blame]33GICV3_SUPPORT_GIC600 := 1
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]34
35# Include GICv3 driver files
36include drivers/arm/gic/v3/gicv3.mk
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]37
Alexei Fedorov84f1b5d2020-03-23 18:45:17 +0000[diff] [blame]38ENT_GIC_SOURCES := ${GICV3_SOURCES} \
39 plat/common/plat_gicv3.c \
40 plat/arm/common/arm_gicv3.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]41
Aditya Angadi502d0ac2020-11-18 08:27:15 +0530[diff] [blame]42PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/aarch64/sgi_helper.S
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]43
Aditya Angadi20b48412019-04-16 11:29:14 +0530[diff] [blame]44BL1_SOURCES += ${INTERCONNECT_SOURCES} \
45 drivers/arm/sbsa/sbsa.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]46
Nishant Sharma289f7822021-11-30 09:31:48 +0000[diff] [blame]47BL2_SOURCES += ${CSS_ENT_BASE}/sgi_image_load.c \
48 drivers/arm/css/sds/sds.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]49
Chandni Cherukuria3f66132018-08-10 11:17:58 +0530[diff] [blame]50BL31_SOURCES += ${INTERCONNECT_SOURCES} \
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]51 ${ENT_GIC_SOURCES} \
52 ${CSS_ENT_BASE}/sgi_bl31_setup.c \
Chandni Cherukuria5d44ec2018-08-14 15:25:34 +0530[diff] [blame]53 ${CSS_ENT_BASE}/sgi_topology.c
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]54
Sughosh Ganu18f513d2018-05-16 17:22:35 +0530[diff] [blame]55ifeq (${RAS_EXTENSION},1)
56BL31_SOURCES += ${CSS_ENT_BASE}/sgi_ras.c
57endif
58
Deepak Pandeyb0971f92018-05-25 12:43:30 +0530[diff] [blame]59ifneq (${RESET_TO_BL31},0)
Sandrine Bailleux1e32d322019-01-07 15:35:37 +0100[diff] [blame]60 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Deepak Pandeyb0971f92018-05-25 12:43:30 +0530[diff] [blame]61 Please set RESET_TO_BL31 to 0.")
62endif
63
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]64$(eval $(call add_define,SGI_PLAT))
65
Vijayenthiran Subramaniambc489912019-12-26 17:45:58 +0530[diff] [blame]66$(eval $(call add_define,CSS_SGI_CHIP_COUNT))
67
Aditya Angadi06402222021-03-20 12:06:15 +0530[diff] [blame]68$(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT))
69
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]70override CSS_LOAD_SCP_IMAGES := 0
71override NEED_BL2U := no
72override ARM_BL31_IN_DRAM := 1
Sudipto Paulc4510102018-04-16 17:46:50 +0530[diff] [blame]73override ARM_PLAT_MT := 1
Pranav Madhu4c474322021-04-20 12:01:46 +0530[diff] [blame]74override PSCI_EXTENDED_STATE_ID := 1
75override ARM_RECOM_STATE_ID_ENC := 1
Nariman Poushin0ece80f2018-02-26 06:52:04 +0000[diff] [blame]76
77# System coherency is managed in hardware
78HW_ASSISTED_COHERENCY := 1
79
80# When building for systems with hardware-assisted coherency, there's no need to
81# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
82USE_COHERENT_MEM := 0
83
84include plat/arm/common/arm_common.mk
85include plat/arm/css/common/css_common.mk
86include plat/arm/soc/common/soc_css.mk
87include plat/arm/board/common/board_common.mk