| jason-ch chen | fa82b9b | 2021-11-16 09:48:20 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef SLEEP_DEF_H |
| 8 | #define SLEEP_DEF_H |
| 9 | |
| 10 | /* |
| 11 | * Auto generated by DE, please DO NOT modify this file directly. |
| 12 | */ |
| 13 | |
| 14 | /* --- SPM Flag Define --- */ |
| 15 | #define SPM_FLAG_DISABLE_CPU_PDN (1U << 0) |
| 16 | #define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1) |
| 17 | #define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2) |
| 18 | #define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3) |
| 19 | #define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4) |
| 20 | #define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5) |
| 21 | #define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6) |
| 22 | #define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7) |
| 23 | #define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8) |
| 24 | #define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9) |
| 25 | #define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) |
| 26 | #define SPM_FLAG_SSPM_INFRA_SLEEP_MODE (1U << 11) |
| 27 | #define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12) |
| 28 | #define SPM_FLAG_USE_SRCCLKENO2 (1U << 13) |
| 29 | #define SPM_FLAG_RESERVED_BIT14 (1U << 14) |
| 30 | #define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15) |
| 31 | #define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16) |
| 32 | #define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17) |
| 33 | #define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18) |
| 34 | #define SPM_FLAG_RESERVED_BIT19 (1U << 19) |
| 35 | #define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20) |
| 36 | #define SPM_FLAG_RESERVED_BIT21 (1U << 21) |
| 37 | #define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22) |
| 38 | #define SPM_FLAG_DISABLE_SRAM_EVENT (1U << 23) |
| 39 | #define SPM_FLAG_RESERVED_BIT24 (1U << 24) |
| 40 | #define SPM_FLAG_RESERVED_BIT25 (1U << 25) |
| 41 | #define SPM_FLAG_RESERVED_BIT26 (1U << 26) |
| 42 | #define SPM_FLAG_DDREN_STATE (1U << 27) |
| 43 | #define SPM_FLAG_VTCXO_STATE (1U << 28) |
| 44 | #define SPM_FLAG_INFRA_STATE (1U << 29) |
| 45 | #define SPM_FLAG_VRF18_STATE (1U << 30) |
| 46 | #define SPM_FLAG_APSRC_STATE (1U << 31) |
| 47 | #define SPM_FLAG_SYSTEM_POWER_STATE (1U << 28) |
| 48 | /* --- SPM Flag1 Define --- */ |
| 49 | #define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0) |
| 50 | #define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1) |
| 51 | #define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2) |
| 52 | #define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3) |
| 53 | #define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4) |
| 54 | #define SPM_FLAG1_RESERVED_BIT5 (1U << 5) |
| 55 | #define SPM_FLAG1_ENABLE_REKICK (1U << 6) |
| 56 | #define SPM_FLAG1_RESERVED_BIT7 (1U << 7) |
| 57 | #define SPM_FLAG1_RESERVED_BIT8 (1U << 8) |
| 58 | #define SPM_FLAG1_RESERVED_BIT9 (1U << 9) |
| 59 | #define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10) |
| 60 | #define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11) |
| 61 | #define SPM_FLAG1_RESERVED_BIT12 (1U << 12) |
| 62 | #define SPM_FLAG1_RESERVED_BIT13 (1U << 13) |
| 63 | #define SPM_FLAG1_RESERVED_BIT14 (1U << 14) |
| 64 | #define SPM_FLAG1_RESERVED_BIT15 (1U << 15) |
| 65 | #define SPM_FLAG1_RESERVED_BIT16 (1U << 16) |
| 66 | #define SPM_FLAG1_RESERVED_BIT17 (1U << 17) |
| 67 | #define SPM_FLAG1_RESERVED_BIT18 (1U << 18) |
| 68 | #define SPM_FLAG1_RESERVED_BIT19 (1U << 19) |
| 69 | #define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20) |
| 70 | #define SPM_FLAG1_RESERVED_BIT21 (1U << 21) |
| 71 | #define SPM_FLAG1_RESERVED_BIT22 (1U << 22) |
| 72 | #define SPM_FLAG1_RESERVED_BIT23 (1U << 23) |
| 73 | #define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24) |
| 74 | #define SPM_FLAG1_RESERVED_BIT25 (1U << 25) |
| 75 | #define SPM_FLAG1_RESERVED_BIT26 (1U << 26) |
| 76 | #define SPM_FLAG1_RESERVED_BIT27 (1U << 27) |
| 77 | #define SPM_FLAG1_RESERVED_BIT28 (1U << 28) |
| 78 | #define SPM_FLAG1_RESERVED_BIT29 (1U << 29) |
| 79 | #define SPM_FLAG1_RESERVED_BIT30 (1U << 30) |
| 80 | #define SPM_FLAG1_ENABLE_MCUPM_OFF (1U << 31) |
| 81 | /* --- SPM DEBUG Define --- */ |
| 82 | #define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0) |
| 83 | #define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1) |
| 84 | #define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2) |
| 85 | #define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3) |
| 86 | #define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4) |
| 87 | #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5) |
| 88 | #define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6) |
| 89 | #define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7) |
| 90 | #define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8) |
| 91 | #define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9) |
| 92 | #define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10) |
| 93 | #define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11) |
| 94 | #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12) |
| 95 | #define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13) |
| 96 | #define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14) |
| 97 | #define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15) |
| 98 | #define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16) |
| 99 | #define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17) |
| 100 | #define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18) |
| 101 | #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19) |
| 102 | #define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20) |
| 103 | #define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21) |
| 104 | #define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22) |
| 105 | #define SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT (1U << 23) |
| 106 | #define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27) |
| 107 | #define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28) |
| 108 | #define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29) |
| 109 | #define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30) |
| 110 | #define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31) |
| 111 | /* --- SPM DEBUG1 Define --- */ |
| 112 | #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0) |
| 113 | #define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1) |
| 114 | #define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2) |
| 115 | #define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3) |
| 116 | #define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4) |
| 117 | #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5) |
| 118 | #define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6) |
| 119 | #define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7) |
| 120 | #define SPM_DBG1_RESERVED_BIT8 (1U << 8) |
| 121 | #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11) |
| 122 | #define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12) |
| 123 | #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13) |
| 124 | #define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14) |
| 125 | #define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15) |
| 126 | #define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16) |
| 127 | #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17) |
| 128 | #define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18) |
| 129 | #define SPM_DBG1_DEBUG_IDX_MCUPM_WAKE_IRQ (1U << 19) |
| 130 | #define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20) |
| 131 | #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23) |
| 132 | #define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24) |
| 133 | #define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25) |
| 134 | #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26) |
| 135 | #define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27) |
| 136 | #define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28) |
| 137 | #define SPM_DBG1_DEBUG_IDX_SPM_TIMER_RST_DVFS (1U << 29) |
| 138 | #define SPM_DBG1_DEBUG_IDX_SPM_DISABLE_DDREN_EVENT (1U << 30) |
| 139 | #define MCUPM_RESTORE (1U << 31) |
| 140 | |
| 141 | /* Macro and Inline */ |
| 142 | #define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U) |
| 143 | #define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U) |
| 144 | #define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U) |
| 145 | |
| 146 | #endif /* SLEEP_DEF_H */ |