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git01.mediatek.com / filogic / atf / f138bde744271725700a906aee5d8e9a5d4ddbe1 / . / include / lib / cpus / aarch64 / neoverse_demeter.h
blob: f1afae7b02cb517ef8936c7c0024d6307e34af3b [file] [log] [blame]
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]1/*
Bipin Ravi32464ba2022-05-06 16:02:30 -0500[diff] [blame]2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
johpow011ec298c2021-10-15 12:02:36 -0500[diff] [blame]7#ifndef NEOVERSE_DEMETER_H
8#define NEOVERSE_DEMETER_H
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]9
johpow011ec298c2021-10-15 12:02:36 -0500[diff] [blame]10#define NEOVERSE_DEMETER_MIDR U(0x410FD4F0)
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]11
Bipin Ravi32464ba2022-05-06 16:02:30 -0500[diff] [blame]12/* Neoverse Demeter loop count for CVE-2022-23960 mitigation */
13#define NEOVERSE_DEMETER_BHB_LOOP_COUNT U(132)
14
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]15/*******************************************************************************
16 * CPU Extended Control register specific definitions
17 ******************************************************************************/
johpow011ec298c2021-10-15 12:02:36 -0500[diff] [blame]18#define NEOVERSE_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]19
20/*******************************************************************************
21 * CPU Power Control register specific definitions
22 ******************************************************************************/
johpow011ec298c2021-10-15 12:02:36 -0500[diff] [blame]23#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
24#define NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
johpow01f0c8b262021-07-07 17:06:07 -0500[diff] [blame]25
johpow011ec298c2021-10-15 12:02:36 -0500[diff] [blame]26#endif /* NEOVERSE_DEMETER_H */