Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 1 | /* |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 2 | * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 7 | #include <assert.h> |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 8 | #include <cdefs.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <stdbool.h> |
| 10 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 11 | #include "../amu_private.h" |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 12 | #include <arch.h> |
| 13 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <lib/el3_runtime/pubsub_events.h> |
| 15 | #include <lib/extensions/amu.h> |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 16 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 17 | #include <plat/common/platform.h> |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 18 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 19 | struct amu_ctx { |
| 20 | uint64_t group0_cnts[AMU_GROUP0_MAX_COUNTERS]; |
| 21 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 22 | uint64_t group1_cnts[AMU_GROUP1_MAX_COUNTERS]; |
| 23 | #endif |
| 24 | |
| 25 | uint16_t group0_enable; |
| 26 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 27 | uint16_t group1_enable; |
| 28 | #endif |
| 29 | }; |
| 30 | |
| 31 | static struct amu_ctx amu_ctxs_[PLATFORM_CORE_COUNT]; |
| 32 | |
| 33 | CASSERT((sizeof(amu_ctxs_[0].group0_enable) * CHAR_BIT) <= AMU_GROUP0_MAX_COUNTERS, |
| 34 | amu_ctx_group0_enable_cannot_represent_all_group0_counters); |
| 35 | |
| 36 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 37 | CASSERT((sizeof(amu_ctxs_[0].group1_enable) * CHAR_BIT) <= AMU_GROUP1_MAX_COUNTERS, |
| 38 | amu_ctx_group1_enable_cannot_represent_all_group1_counters); |
| 39 | #endif |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 40 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 41 | static inline __unused uint32_t read_id_pfr0_amu(void) |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 42 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 43 | return (read_id_pfr0() >> ID_PFR0_AMU_SHIFT) & |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 44 | ID_PFR0_AMU_MASK; |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 45 | } |
| 46 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 47 | static inline __unused void write_hcptr_tam(uint32_t value) |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 48 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 49 | write_hcptr((read_hcptr() & ~TAM_BIT) | |
| 50 | ((value << TAM_SHIFT) & TAM_BIT)); |
| 51 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 52 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 53 | static inline __unused void write_amcr_cg1rz(uint32_t value) |
| 54 | { |
| 55 | write_amcr((read_amcr() & ~AMCR_CG1RZ_BIT) | |
| 56 | ((value << AMCR_CG1RZ_SHIFT) & AMCR_CG1RZ_BIT)); |
| 57 | } |
| 58 | |
| 59 | static inline __unused uint32_t read_amcfgr_ncg(void) |
| 60 | { |
| 61 | return (read_amcfgr() >> AMCFGR_NCG_SHIFT) & |
| 62 | AMCFGR_NCG_MASK; |
| 63 | } |
| 64 | |
Chris Kay | a40141d | 2021-05-25 12:33:18 +0100 | [diff] [blame] | 65 | static inline __unused uint32_t read_amcgcr_cg0nc(void) |
| 66 | { |
| 67 | return (read_amcgcr() >> AMCGCR_CG0NC_SHIFT) & |
| 68 | AMCGCR_CG0NC_MASK; |
| 69 | } |
| 70 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 71 | static inline __unused uint32_t read_amcgcr_cg1nc(void) |
| 72 | { |
| 73 | return (read_amcgcr() >> AMCGCR_CG1NC_SHIFT) & |
| 74 | AMCGCR_CG1NC_MASK; |
| 75 | } |
| 76 | |
| 77 | static inline __unused uint32_t read_amcntenset0_px(void) |
| 78 | { |
| 79 | return (read_amcntenset0() >> AMCNTENSET0_Pn_SHIFT) & |
| 80 | AMCNTENSET0_Pn_MASK; |
| 81 | } |
| 82 | |
| 83 | static inline __unused uint32_t read_amcntenset1_px(void) |
| 84 | { |
| 85 | return (read_amcntenset1() >> AMCNTENSET1_Pn_SHIFT) & |
| 86 | AMCNTENSET1_Pn_MASK; |
| 87 | } |
| 88 | |
| 89 | static inline __unused void write_amcntenset0_px(uint32_t px) |
| 90 | { |
| 91 | uint32_t value = read_amcntenset0(); |
| 92 | |
| 93 | value &= ~AMCNTENSET0_Pn_MASK; |
| 94 | value |= (px << AMCNTENSET0_Pn_SHIFT) & |
| 95 | AMCNTENSET0_Pn_MASK; |
| 96 | |
| 97 | write_amcntenset0(value); |
| 98 | } |
| 99 | |
| 100 | static inline __unused void write_amcntenset1_px(uint32_t px) |
| 101 | { |
| 102 | uint32_t value = read_amcntenset1(); |
| 103 | |
| 104 | value &= ~AMCNTENSET1_Pn_MASK; |
| 105 | value |= (px << AMCNTENSET1_Pn_SHIFT) & |
| 106 | AMCNTENSET1_Pn_MASK; |
| 107 | |
| 108 | write_amcntenset1(value); |
| 109 | } |
| 110 | |
| 111 | static inline __unused void write_amcntenclr0_px(uint32_t px) |
| 112 | { |
| 113 | uint32_t value = read_amcntenclr0(); |
| 114 | |
| 115 | value &= ~AMCNTENCLR0_Pn_MASK; |
| 116 | value |= (px << AMCNTENCLR0_Pn_SHIFT) & AMCNTENCLR0_Pn_MASK; |
| 117 | |
| 118 | write_amcntenclr0(value); |
| 119 | } |
| 120 | |
| 121 | static inline __unused void write_amcntenclr1_px(uint32_t px) |
| 122 | { |
| 123 | uint32_t value = read_amcntenclr1(); |
| 124 | |
| 125 | value &= ~AMCNTENCLR1_Pn_MASK; |
| 126 | value |= (px << AMCNTENCLR1_Pn_SHIFT) & AMCNTENCLR1_Pn_MASK; |
| 127 | |
| 128 | write_amcntenclr1(value); |
| 129 | } |
| 130 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 131 | static __unused bool amu_supported(void) |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 132 | { |
| 133 | return read_id_pfr0_amu() >= ID_PFR0_AMU_V1; |
| 134 | } |
| 135 | |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 136 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 137 | static __unused bool amu_group1_supported(void) |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 138 | { |
| 139 | return read_amcfgr_ncg() > 0U; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 140 | } |
| 141 | #endif |
| 142 | |
| 143 | /* |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 144 | * Enable counters. This function is meant to be invoked by the context |
| 145 | * management library before exiting from EL3. |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 146 | */ |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 147 | void amu_enable(bool el2_unused) |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 148 | { |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 149 | uint32_t id_pfr0_amu; /* AMU version */ |
| 150 | |
| 151 | uint32_t amcfgr_ncg; /* Number of counter groups */ |
| 152 | uint32_t amcgcr_cg0nc; /* Number of group 0 counters */ |
| 153 | |
| 154 | uint32_t amcntenset0_px = 0x0; /* Group 0 enable mask */ |
| 155 | uint32_t amcntenset1_px = 0x0; /* Group 1 enable mask */ |
| 156 | |
| 157 | id_pfr0_amu = read_id_pfr0_amu(); |
| 158 | if (id_pfr0_amu == ID_PFR0_AMU_NOT_SUPPORTED) { |
| 159 | /* |
| 160 | * If the AMU is unsupported, nothing needs to be done. |
| 161 | */ |
| 162 | |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 163 | return; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 164 | } |
| 165 | |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 166 | if (el2_unused) { |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 167 | /* |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 168 | * HCPTR.TAM: Set to zero so any accesses to the Activity |
| 169 | * Monitor registers do not trap to EL2. |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 170 | */ |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 171 | write_hcptr_tam(0U); |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 172 | } |
Dimitris Papastamos | 525c37a | 2017-11-13 09:49:45 +0000 | [diff] [blame] | 173 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 174 | /* |
| 175 | * Retrieve the number of architected counters. All of these counters |
| 176 | * are enabled by default. |
| 177 | */ |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 178 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 179 | amcgcr_cg0nc = read_amcgcr_cg0nc(); |
| 180 | amcntenset0_px = (UINT32_C(1) << (amcgcr_cg0nc)) - 1U; |
| 181 | |
| 182 | assert(amcgcr_cg0nc <= AMU_AMCGCR_CG0NC_MAX); |
| 183 | |
| 184 | /* |
| 185 | * Enable the requested counters. |
| 186 | */ |
| 187 | |
| 188 | write_amcntenset0_px(amcntenset0_px); |
| 189 | |
| 190 | amcfgr_ncg = read_amcfgr_ncg(); |
| 191 | if (amcfgr_ncg > 0U) { |
| 192 | write_amcntenset1_px(amcntenset1_px); |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 193 | } |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 194 | |
| 195 | /* Initialize FEAT_AMUv1p1 features if present. */ |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 196 | if (id_pfr0_amu < ID_PFR0_AMU_V1P1) { |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 197 | return; |
| 198 | } |
| 199 | |
| 200 | #if AMU_RESTRICT_COUNTERS |
| 201 | /* |
| 202 | * FEAT_AMUv1p1 adds a register field to restrict access to group 1 |
| 203 | * counters at all but the highest implemented EL. This is controlled |
| 204 | * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system |
| 205 | * register reads at lower ELs return zero. Reads from the memory |
| 206 | * mapped view are unaffected. |
| 207 | */ |
| 208 | VERBOSE("AMU group 1 counter access restricted.\n"); |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 209 | write_amcr_cg1rz(1U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 210 | #else |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 211 | write_amcr_cg1rz(0U); |
johpow01 | fa59c6f | 2020-10-02 13:41:11 -0500 | [diff] [blame] | 212 | #endif |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | /* Read the group 0 counter identified by the given `idx`. */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 216 | static uint64_t amu_group0_cnt_read(unsigned int idx) |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 217 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 218 | assert(amu_supported()); |
Chris Kay | a40141d | 2021-05-25 12:33:18 +0100 | [diff] [blame] | 219 | assert(idx < read_amcgcr_cg0nc()); |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 220 | |
| 221 | return amu_group0_cnt_read_internal(idx); |
| 222 | } |
| 223 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 224 | /* Write the group 0 counter identified by the given `idx` with `val` */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 225 | static void amu_group0_cnt_write(unsigned int idx, uint64_t val) |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 226 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 227 | assert(amu_supported()); |
Chris Kay | a40141d | 2021-05-25 12:33:18 +0100 | [diff] [blame] | 228 | assert(idx < read_amcgcr_cg0nc()); |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 229 | |
| 230 | amu_group0_cnt_write_internal(idx, val); |
| 231 | isb(); |
| 232 | } |
| 233 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 234 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 235 | /* Read the group 1 counter identified by the given `idx` */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 236 | static uint64_t amu_group1_cnt_read(unsigned int idx) |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 237 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 238 | assert(amu_supported()); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 239 | assert(amu_group1_supported()); |
Chris Kay | da81914 | 2021-05-25 15:24:18 +0100 | [diff] [blame] | 240 | assert(idx < read_amcgcr_cg1nc()); |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 241 | |
| 242 | return amu_group1_cnt_read_internal(idx); |
| 243 | } |
| 244 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 245 | /* Write the group 1 counter identified by the given `idx` with `val` */ |
Chris Kay | f13c6b5 | 2021-05-24 21:00:07 +0100 | [diff] [blame] | 246 | static void amu_group1_cnt_write(unsigned int idx, uint64_t val) |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 247 | { |
Chris Kay | a5fde28 | 2021-05-26 11:58:23 +0100 | [diff] [blame] | 248 | assert(amu_supported()); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 249 | assert(amu_group1_supported()); |
Chris Kay | da81914 | 2021-05-25 15:24:18 +0100 | [diff] [blame] | 250 | assert(idx < read_amcgcr_cg1nc()); |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 251 | |
| 252 | amu_group1_cnt_write_internal(idx, val); |
| 253 | isb(); |
| 254 | } |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 255 | #endif |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 256 | |
| 257 | static void *amu_context_save(const void *arg) |
| 258 | { |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 259 | uint32_t i; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 260 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 261 | unsigned int core_pos; |
| 262 | struct amu_ctx *ctx; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 263 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 264 | uint32_t id_pfr0_amu; /* AMU version */ |
| 265 | uint32_t amcgcr_cg0nc; /* Number of group 0 counters */ |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 266 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 267 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 268 | uint32_t amcfgr_ncg; /* Number of counter groups */ |
| 269 | uint32_t amcgcr_cg1nc; /* Number of group 1 counters */ |
| 270 | #endif |
| 271 | |
| 272 | id_pfr0_amu = read_id_pfr0_amu(); |
| 273 | if (id_pfr0_amu == ID_PFR0_AMU_NOT_SUPPORTED) { |
| 274 | return (void *)0; |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 275 | } |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 276 | |
| 277 | core_pos = plat_my_core_pos(); |
| 278 | ctx = &amu_ctxs_[core_pos]; |
| 279 | |
| 280 | amcgcr_cg0nc = read_amcgcr_cg0nc(); |
| 281 | |
| 282 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 283 | amcfgr_ncg = read_amcfgr_ncg(); |
| 284 | amcgcr_cg1nc = (amcfgr_ncg > 0U) ? read_amcgcr_cg1nc() : 0U; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 285 | #endif |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 286 | |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 287 | /* |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 288 | * Disable all AMU counters. |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 289 | */ |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 290 | |
| 291 | ctx->group0_enable = read_amcntenset0_px(); |
| 292 | write_amcntenclr0_px(ctx->group0_enable); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 293 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 294 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 295 | if (amcfgr_ncg > 0U) { |
| 296 | ctx->group1_enable = read_amcntenset1_px(); |
| 297 | write_amcntenclr1_px(ctx->group1_enable); |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 298 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 299 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 300 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 301 | /* |
| 302 | * Save the counters to the local context. |
| 303 | */ |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 304 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 305 | isb(); /* Ensure counters have been stopped */ |
| 306 | |
| 307 | for (i = 0U; i < amcgcr_cg0nc; i++) { |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 308 | ctx->group0_cnts[i] = amu_group0_cnt_read(i); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 309 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 310 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 311 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 312 | for (i = 0U; i < amcgcr_cg1nc; i++) { |
| 313 | ctx->group1_cnts[i] = amu_group1_cnt_read(i); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 314 | } |
| 315 | #endif |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 316 | |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 317 | return (void *)0; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | static void *amu_context_restore(const void *arg) |
| 321 | { |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 322 | uint32_t i; |
| 323 | |
| 324 | unsigned int core_pos; |
| 325 | struct amu_ctx *ctx; |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 326 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 327 | uint32_t id_pfr0_amu; /* AMU version */ |
| 328 | |
| 329 | uint32_t amcfgr_ncg; /* Number of counter groups */ |
| 330 | uint32_t amcgcr_cg0nc; /* Number of group 0 counters */ |
| 331 | |
| 332 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 333 | uint32_t amcgcr_cg1nc; /* Number of group 1 counters */ |
| 334 | #endif |
| 335 | |
| 336 | id_pfr0_amu = read_id_pfr0_amu(); |
| 337 | if (id_pfr0_amu == ID_PFR0_AMU_NOT_SUPPORTED) { |
| 338 | return (void *)0; |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 339 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 340 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 341 | core_pos = plat_my_core_pos(); |
| 342 | ctx = &amu_ctxs_[core_pos]; |
| 343 | |
| 344 | amcfgr_ncg = read_amcfgr_ncg(); |
| 345 | amcgcr_cg0nc = read_amcgcr_cg0nc(); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 346 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 347 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 348 | amcgcr_cg1nc = (amcfgr_ncg > 0U) ? read_amcgcr_cg1nc() : 0U; |
| 349 | #endif |
| 350 | |
| 351 | /* |
| 352 | * Sanity check that all counters were disabled when the context was |
| 353 | * previously saved. |
| 354 | */ |
| 355 | |
| 356 | assert(read_amcntenset0_px() == 0U); |
| 357 | |
| 358 | if (amcfgr_ncg > 0U) { |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 359 | assert(read_amcntenset1_px() == 0U); |
| 360 | } |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 361 | |
| 362 | /* |
| 363 | * Restore the counter values from the local context. |
| 364 | */ |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 365 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 366 | for (i = 0U; i < amcgcr_cg0nc; i++) { |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 367 | amu_group0_cnt_write(i, ctx->group0_cnts[i]); |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 368 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 369 | |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 370 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 371 | for (i = 0U; i < amcgcr_cg1nc; i++) { |
| 372 | amu_group1_cnt_write(i, ctx->group1_cnts[i]); |
| 373 | } |
| 374 | #endif |
| 375 | |
| 376 | /* |
| 377 | * Re-enable counters that were disabled during context save. |
| 378 | */ |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 379 | |
Chris Kay | 26a7961 | 2021-05-24 20:35:26 +0100 | [diff] [blame] | 380 | write_amcntenset0_px(ctx->group0_enable); |
| 381 | |
| 382 | #if ENABLE_AMU_AUXILIARY_COUNTERS |
| 383 | if (amcfgr_ncg > 0U) { |
| 384 | write_amcntenset1_px(ctx->group1_enable); |
Chris Kay | 925fda4 | 2021-05-25 10:42:56 +0100 | [diff] [blame] | 385 | } |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 386 | #endif |
| 387 | |
Antonio Nino Diaz | 033b4bb | 2018-10-25 16:52:26 +0100 | [diff] [blame] | 388 | return (void *)0; |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 389 | } |
Dimitris Papastamos | eaf3e6d | 2017-11-28 13:47:06 +0000 | [diff] [blame] | 390 | |
| 391 | SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save); |
| 392 | SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, amu_context_restore); |