| Jiafei Pan | f0b86b1 | 2021-10-21 16:14:18 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2022 NXP | ||||
| 3 | * | ||||
| 4 | * SPDX-License-Identifier: BSD-3-Clause | ||||
| 5 | */ | ||||
| 6 | |||||
| 7 | #ifndef IFC_NAND_H | ||||
| 8 | #define IFC_NAND_H | ||||
| 9 | |||||
| 10 | #define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */ | ||||
| 11 | |||||
| 12 | int ifc_nand_init(uintptr_t *block_dev_spec, | ||||
| 13 | uintptr_t ifc_region_addr, | ||||
| 14 | uintptr_t ifc_register_addr, | ||||
| 15 | size_t ifc_sram_size, | ||||
| 16 | uintptr_t ifc_nand_blk_offset, | ||||
| 17 | size_t ifc_nand_blk_size); | ||||
| 18 | |||||
| 19 | #endif /*IFC_NAND_H*/ | ||||