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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Manish V Badarkhe6e6df442023-03-20 14:58:06 +00002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +01006#ifndef PLAT_ARM_H
7#define PLAT_ARM_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Louis Mayencourt70d7c092020-01-29 11:42:31 +00009#include <stdbool.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <drivers/arm/tzc_common.h>
13#include <lib/bakery_lock.h>
14#include <lib/cassert.h>
15#include <lib/el3_runtime/cpu_data.h>
16#include <lib/spinlock.h>
17#include <lib/utils_def.h>
18#include <lib/xlat_tables/xlat_tables_compat.h>
Dan Handley9df48042015-03-19 18:58:55 +000019
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010020/*******************************************************************************
21 * Forward declarations
22 ******************************************************************************/
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010023struct meminfo;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010024struct image_info;
Soby Mathew96a1c6b2018-01-15 14:45:33 +000025struct bl_params;
Sandrine Bailleuxf402a522016-09-15 10:09:53 +010026
Summer Qin5ce394c2018-03-12 11:28:26 +080027typedef struct arm_tzc_regions_info {
28 unsigned long long base;
29 unsigned long long end;
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010030 unsigned int sec_attr;
Summer Qin5ce394c2018-03-12 11:28:26 +080031 unsigned int nsaid_permissions;
32} arm_tzc_regions_info_t;
33
34/*******************************************************************************
35 * Default mapping definition of the TrustZone Controller for ARM standard
36 * platforms.
37 * Configure:
38 * - Region 0 with no access;
39 * - Region 1 with secure access only;
40 * - the remaining DRAM regions access from the given Non-Secure masters.
41 ******************************************************************************/
Manish V Badarkhe19c72182023-09-01 07:54:33 +010042
43#if ENABLE_RME
44#define ARM_TZC_RME_REGIONS_DEF \
45 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
46 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
47 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
48 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
49 /* Realm and Shared area share the same PAS */ \
50 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
51 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
52 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
53 PLAT_ARM_TZC_NS_DEV_ACCESS}
54#endif
55
Nishant Sharmae78ef3d2023-10-12 10:37:54 +010056#if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
Summer Qin5ce394c2018-03-12 11:28:26 +080057#define ARM_TZC_REGIONS_DEF \
Zelalem Awekec43c5632021-07-12 23:41:05 -050058 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
Summer Qin5ce394c2018-03-12 11:28:26 +080059 TZC_REGION_S_RDWR, 0}, \
60 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
61 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
62 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
63 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +010064 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \
65 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \
Summer Qin5ce394c2018-03-12 11:28:26 +080066 PLAT_ARM_TZC_NS_DEV_ACCESS}
67
Zelalem Awekec43c5632021-07-12 23:41:05 -050068#elif ENABLE_RME
Manish V Badarkhe19c72182023-09-01 07:54:33 +010069#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
70MEASURED_BOOT
71#define ARM_TZC_REGIONS_DEF \
72 ARM_TZC_RME_REGIONS_DEF, \
73 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \
74 TZC_REGION_S_RDWR, 0}
75#else
76#define ARM_TZC_REGIONS_DEF \
77 ARM_TZC_RME_REGIONS_DEF
78#endif
Zelalem Awekec43c5632021-07-12 23:41:05 -050079
Summer Qin5ce394c2018-03-12 11:28:26 +080080#else
81#define ARM_TZC_REGIONS_DEF \
Zelalem Awekec43c5632021-07-12 23:41:05 -050082 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
Summer Qin5ce394c2018-03-12 11:28:26 +080083 TZC_REGION_S_RDWR, 0}, \
84 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
85 PLAT_ARM_TZC_NS_DEV_ACCESS}, \
86 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
87 PLAT_ARM_TZC_NS_DEV_ACCESS}
88#endif
89
Chris Kay2b54c0c2018-05-09 15:46:07 +010090#define ARM_CASSERT_MMAP \
91 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
92 assert_plat_arm_mmap_mismatch); \
93 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \
94 <= MAX_MMAP_REGIONS, \
Dan Handley9df48042015-03-19 18:58:55 +000095 assert_max_mmap_regions);
96
Roberto Vargase3adc372018-05-23 09:27:06 +010097void arm_setup_romlib(void);
98
Julius Werner8e0ef0f2019-07-09 14:02:43 -070099#if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32))
Dan Handley9df48042015-03-19 18:58:55 +0000100/*
101 * Use this macro to instantiate lock before it is used in below
102 * arm_lock_xxx() macros
103 */
Sandrine Bailleuxceb258e2018-07-11 13:59:18 +0200104#define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock)
Soby Mathewea26bad2016-11-14 12:25:45 +0000105#define ARM_LOCK_GET_INSTANCE (&arm_lock)
Roberto Vargas00996942017-11-13 13:41:58 +0000106
107#if !HW_ASSISTED_COHERENCY
108#define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock)
109#else
110#define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock
111#endif
112#define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock)
113
Dan Handley9df48042015-03-19 18:58:55 +0000114/*
115 * These are wrapper macros to the Coherent Memory Bakery Lock API.
116 */
117#define arm_lock_init() bakery_lock_init(&arm_lock)
118#define arm_lock_get() bakery_lock_get(&arm_lock)
119#define arm_lock_release() bakery_lock_release(&arm_lock)
120
121#else
122
Dan Handley9df48042015-03-19 18:58:55 +0000123/*
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000124 * Empty macros for all other BL stages other than BL31 and BL32
Dan Handley9df48042015-03-19 18:58:55 +0000125 */
Jeenu Viswambharan749d25b2017-08-23 14:12:59 +0100126#define ARM_INSTANTIATE_LOCK static int arm_lock __unused
Soby Mathewea26bad2016-11-14 12:25:45 +0000127#define ARM_LOCK_GET_INSTANCE 0
Dan Handley9df48042015-03-19 18:58:55 +0000128#define arm_lock_init()
129#define arm_lock_get()
130#define arm_lock_release()
131
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700132#endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */
Dan Handley9df48042015-03-19 18:58:55 +0000133
Soby Mathew7799cf72015-04-16 14:49:09 +0100134#if ARM_RECOM_STATE_ID_ENC
135/*
136 * Macros used to parse state information from State-ID if it is using the
137 * recommended encoding for State-ID.
138 */
139#define ARM_LOCAL_PSTATE_WIDTH 4
140#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
141
Wing Li05364b92023-01-26 18:33:43 -0800142#if PSCI_OS_INIT_MODE
143#define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \
144 (ARM_LOCAL_PSTATE_WIDTH * \
145 (PLAT_MAX_PWR_LVL + 1)))
146#endif /* __PSCI_OS_INIT_MODE__ */
147
Soby Mathew7799cf72015-04-16 14:49:09 +0100148/* Macros to construct the composite power state */
149
150/* Make composite power state parameter till power level 0 */
151#if PSCI_EXTENDED_STATE_ID
152
153#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
154 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
155#else
156#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
157 (((lvl0_state) << PSTATE_ID_SHIFT) | \
158 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
159 ((type) << PSTATE_TYPE_SHIFT))
160#endif /* __PSCI_EXTENDED_STATE_ID__ */
161
162/* Make composite power state parameter till power level 1 */
163#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
164 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
165 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
166
Soby Mathewa869de12015-05-08 10:18:59 +0100167/* Make composite power state parameter till power level 2 */
168#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
169 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
170 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
171
Soby Mathew7799cf72015-04-16 14:49:09 +0100172#endif /* __ARM_RECOM_STATE_ID_ENC__ */
173
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000174/* ARM State switch error codes */
175#define STATE_SW_E_PARAM (-2)
176#define STATE_SW_E_DENIED (-3)
Dan Handley9df48042015-03-19 18:58:55 +0000177
Max Shvetsov06dba292019-12-06 11:50:12 +0000178/* plat_get_rotpk_info() flags */
laurenw-arm02169532023-08-15 14:57:56 -0500179#define ARM_ROTPK_REGS_ID 1
180#define ARM_ROTPK_DEVEL_RSA_ID 2
181#define ARM_ROTPK_DEVEL_ECDSA_ID 3
laurenw-arm055199b2022-10-28 11:26:32 -0500182#define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4
laurenw-arm02169532023-08-15 14:57:56 -0500183#define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5
184
185#define ARM_USE_DEVEL_ROTPK \
186 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \
187 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \
188 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \
189 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID)
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000190
Dan Handley9df48042015-03-19 18:58:55 +0000191/* IO storage utility functions */
Louis Mayencourt7d24ce12020-01-29 14:43:06 +0000192int arm_io_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000193
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000194/* Set image specification in IO block policy */
Manish V Badarkhed2f0a7a2021-06-25 23:43:33 +0100195int arm_set_image_source(unsigned int image_id, const char *part_name,
196 uintptr_t *dev_handle, uintptr_t *image_spec);
197void arm_set_fip_addr(uint32_t active_fw_bank_idx);
Manish V Badarkhedd6f2522021-02-22 17:30:17 +0000198
Dan Handley9df48042015-03-19 18:58:55 +0000199/* Security utility functions */
Suyash Pathakb71a9e62020-02-04 13:55:20 +0530200void arm_tzc400_setup(uintptr_t tzc_base,
201 const arm_tzc_regions_info_t *tzc_regions);
Vikram Kanigiri510d87b2016-01-29 12:32:58 +0000202struct tzc_dmc500_driver_data;
Summer Qin5ce394c2018-03-12 11:28:26 +0800203void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
204 const arm_tzc_regions_info_t *tzc_regions);
Dan Handley9df48042015-03-19 18:58:55 +0000205
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +0100206/* Console utility functions */
207void arm_console_boot_init(void);
208void arm_console_boot_end(void);
209void arm_console_runtime_init(void);
210void arm_console_runtime_end(void);
211
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100212/* Systimer utility function */
213void arm_configure_sys_timer(void);
214
Dan Handley9df48042015-03-19 18:58:55 +0000215/* PM utility functions */
Soby Mathewfec4eb72015-07-01 16:16:20 +0100216int arm_validate_power_state(unsigned int power_state,
217 psci_power_state_t *req_state);
Jeenu Viswambharan59424d82017-09-19 09:27:18 +0100218int arm_validate_psci_entrypoint(uintptr_t entrypoint);
Soby Mathew0d9e8522015-07-15 13:36:24 +0100219int arm_validate_ns_entrypoint(uintptr_t entrypoint);
Soby Mathew9ca28062017-10-11 16:08:58 +0100220void arm_system_pwr_domain_save(void);
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100221void arm_system_pwr_domain_resume(void);
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000222int arm_psci_read_mem_protect(int *enabled);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100223int arm_nor_psci_write_mem_protect(int val);
Roberto Vargas550eb082018-01-05 16:00:05 +0000224void arm_nor_psci_do_static_mem_protect(void);
225void arm_nor_psci_do_dyn_mem_protect(void);
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100226int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100227
228/* Topology utility function */
229int arm_check_mpidr(u_register_t mpidr);
Dan Handley9df48042015-03-19 18:58:55 +0000230
231/* BL1 utility functions */
232void arm_bl1_early_platform_setup(void);
233void arm_bl1_platform_setup(void);
234void arm_bl1_plat_arch_setup(void);
235
236/* BL2 utility functions */
Manish V Badarkhe99a8e142020-06-11 22:32:11 +0100237void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout);
Dan Handley9df48042015-03-19 18:58:55 +0000238void arm_bl2_platform_setup(void);
239void arm_bl2_plat_arch_setup(void);
240uint32_t arm_get_spsr_for_bl32_entry(void);
241uint32_t arm_get_spsr_for_bl33_entry(void);
Ambroise Vincentb237bca2019-02-13 15:58:00 +0000242int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000243int arm_bl2_handle_post_image_load(unsigned int image_id);
Sathees Balya90950092018-11-15 14:22:30 +0000244struct bl_params *arm_get_next_bl_params(void);
Dan Handley9df48042015-03-19 18:58:55 +0000245
Roberto Vargas52207802017-11-17 13:22:18 +0000246/* BL2 at EL3 functions */
247void arm_bl2_el3_early_platform_setup(void);
248void arm_bl2_el3_plat_arch_setup(void);
249
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100250/* BL2U utility functions */
251void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
252 void *plat_info);
253void arm_bl2u_platform_setup(void);
254void arm_bl2u_plat_arch_setup(void);
255
Juan Castillo7d199412015-12-14 09:35:25 +0000256/* BL31 utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000257void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
258 uintptr_t hw_config, void *plat_params_from_bl2);
Dan Handley9df48042015-03-19 18:58:55 +0000259void arm_bl31_platform_setup(void);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000260void arm_bl31_plat_runtime_setup(void);
Dan Handley9df48042015-03-19 18:58:55 +0000261void arm_bl31_plat_arch_setup(void);
262
263/* TSP utility functions */
264void arm_tsp_early_platform_setup(void);
265
Soby Mathew7b754182016-07-11 14:15:27 +0100266/* SP_MIN utility functions */
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000267void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
268 uintptr_t hw_config, void *plat_params_from_bl2);
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100269void arm_sp_min_plat_runtime_setup(void);
Madhukar Pappireddyae9677b2020-01-27 13:37:51 -0600270void arm_sp_min_plat_arch_setup(void);
Soby Mathew7b754182016-07-11 14:15:27 +0100271
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100272/* FIP TOC validity check */
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000273bool arm_io_is_toc_valid(void);
Dan Handley9df48042015-03-19 18:58:55 +0000274
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000275/* Utility functions for Dynamic Config */
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000276void arm_bl2_dyn_cfg_init(void);
John Tsichritzisc34341a2018-07-30 13:41:52 +0100277void arm_bl1_set_mbedtls_heap(void);
278int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000279
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000280#if MEASURED_BOOT
Manish V Badarkhe7ca9d652021-09-14 22:41:46 +0100281int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size);
282int arm_set_nt_fw_info(
Alexei Fedorovc7176172020-07-13 12:11:05 +0100283/*
284 * Currently OP-TEE does not support reading DTBs from Secure memory
285 * and this option should be removed when feature is supported.
286 */
287#ifdef SPD_opteed
288 uintptr_t log_addr,
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000289#endif
Alexei Fedorovc7176172020-07-13 12:11:05 +0100290 size_t log_size, uintptr_t *ns_log_addr);
Manish V Badarkhe6e6df442023-03-20 14:58:06 +0000291int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size,
292 size_t log_max_size);
293int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size,
294 size_t *log_max_size);
Alexei Fedorovc7176172020-07-13 12:11:05 +0100295#endif /* MEASURED_BOOT */
Alexei Fedorov25d7c882020-03-20 18:38:55 +0000296
Dan Handley9df48042015-03-19 18:58:55 +0000297/*
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100298 * Free the memory storing initialization code only used during an images boot
299 * time so it can be reclaimed for runtime data
300 */
301void arm_free_init_memory(void);
302
303/*
Petre-Ionut Tudore5a6fef2019-11-07 15:18:03 +0000304 * Make the higher level translation tables read-only
305 */
306void arm_xlat_make_tables_readonly(void);
307
308/*
Dan Handley9df48042015-03-19 18:58:55 +0000309 * Mandatory functions required in ARM standard platforms
310 */
Soby Mathew47e43f22016-02-01 14:04:34 +0000311unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000312void plat_arm_gic_driver_init(void);
Dan Handley9df48042015-03-19 18:58:55 +0000313void plat_arm_gic_init(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000314void plat_arm_gic_cpuif_enable(void);
315void plat_arm_gic_cpuif_disable(void);
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000316void plat_arm_gic_redistif_on(void);
317void plat_arm_gic_redistif_off(void);
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000318void plat_arm_gic_pcpu_init(void);
Soby Mathew9ca28062017-10-11 16:08:58 +0100319void plat_arm_gic_save(void);
320void plat_arm_gic_resume(void);
Dan Handley9df48042015-03-19 18:58:55 +0000321void plat_arm_security_setup(void);
322void plat_arm_pwrc_setup(void);
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000323void plat_arm_interconnect_init(void);
324void plat_arm_interconnect_enter_coherency(void);
325void plat_arm_interconnect_exit_coherency(void);
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100326void plat_arm_program_trusted_mailbox(uintptr_t address);
Louis Mayencourt70d7c092020-01-29 11:42:31 +0000327bool plat_arm_bl1_fwu_needed(void);
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +0100328__dead2 void plat_arm_error_handler(int err);
Manish V Badarkhefcfe4312022-07-12 21:48:04 +0100329__dead2 void plat_arm_system_reset(void);
Dan Handley9df48042015-03-19 18:58:55 +0000330
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530331/*
Max Shvetsov06dba292019-12-06 11:50:12 +0000332 * Optional functions in ARM standard platforms
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530333 */
334void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames);
Sandrine Bailleux7b7a41c2020-02-06 14:34:44 +0100335int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
Max Shvetsov06dba292019-12-06 11:50:12 +0000336 unsigned int *flags);
337int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len,
338 unsigned int *flags);
339int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len,
340 unsigned int *flags);
341int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len,
342 unsigned int *flags);
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530343
Summer Qin93c812f2017-02-28 16:46:17 +0000344#if ARM_PLAT_MT
345unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
346#endif
347
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100348/*
349 * This function is called after loading SCP_BL2 image and it is used to perform
350 * any platform-specific actions required to handle the SCP firmware.
351 */
352int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100353
Dan Handley9df48042015-03-19 18:58:55 +0000354/*
355 * Optional functions required in ARM standard platforms
356 */
357void plat_arm_io_setup(void);
358int plat_arm_get_alt_image_source(
Juan Castillo3a66aca2015-04-13 17:36:19 +0100359 unsigned int image_id,
360 uintptr_t *dev_handle,
361 uintptr_t *image_spec);
Soby Mathewfec4eb72015-07-01 16:16:20 +0100362unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
Vikram Kanigiri07035432015-11-12 18:52:34 +0000363const mmap_region_t *plat_arm_get_mmap(void);
Dan Handley9df48042015-03-19 18:58:55 +0000364
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100365/* Allow platform to override psci_pm_ops during runtime */
366const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
367
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000368/* Execution state switch in ARM platforms */
369int arm_execution_state_switch(unsigned int smc_fid,
370 uint32_t pc_hi,
371 uint32_t pc_lo,
372 uint32_t cookie_hi,
373 uint32_t cookie_lo,
374 void *handle);
375
Soby Mathew6d07e672018-03-01 10:53:33 +0000376/* Optional functions for SP_MIN */
377void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
378 u_register_t arg2, u_register_t arg3);
379
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000380/* global variables */
381extern plat_psci_ops_t plat_arm_psci_pm_ops;
382extern const mmap_region_t plat_arm_mmap[];
Jeenu Viswambharan4542cfe2018-07-19 08:03:46 +0100383extern const unsigned int arm_pm_idle_states[];
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000384
Aditya Angadi20b48412019-04-16 11:29:14 +0530385/* secure watchdog */
386void plat_arm_secure_wdt_start(void);
387void plat_arm_secure_wdt_stop(void);
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500388void plat_arm_secure_wdt_refresh(void);
Aditya Angadi20b48412019-04-16 11:29:14 +0530389
Manish V Badarkhef809c6e2020-02-22 08:43:00 +0000390/* Get SOC-ID of ARM platform */
391uint32_t plat_arm_get_soc_id(void);
392
Antonio Nino Diaz05fdb832018-10-25 16:53:04 +0100393#endif /* PLAT_ARM_H */