| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <mmio.h> |
| 35 | #include <pmc.h> |
| 36 | #include <tegra_def.h> |
| 37 | |
| 38 | /* Module IDs used during power ungate procedure */ |
| 39 | static const int pmc_cpu_powergate_id[4] = { |
| 40 | 0, /* CPU 0 */ |
| 41 | 9, /* CPU 1 */ |
| 42 | 10, /* CPU 2 */ |
| 43 | 11 /* CPU 3 */ |
| 44 | }; |
| 45 | |
| 46 | /******************************************************************************* |
| 47 | * Power ungate CPU to start the boot process. CPU reset vectors must be |
| 48 | * populated before calling this function. |
| 49 | ******************************************************************************/ |
| 50 | void tegra_pmc_cpu_on(int cpu) |
| 51 | { |
| 52 | uint32_t val; |
| 53 | |
| 54 | /* |
| 55 | * The PMC deasserts the START bit when it starts the power |
| 56 | * ungate process. Loop till no power toggle is in progress. |
| 57 | */ |
| 58 | do { |
| 59 | val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); |
| 60 | } while (val & PMC_TOGGLE_START); |
| 61 | |
| 62 | /* |
| 63 | * Start the power ungate procedure |
| 64 | */ |
| 65 | val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; |
| 66 | tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); |
| 67 | |
| 68 | /* |
| 69 | * The PMC deasserts the START bit when it starts the power |
| 70 | * ungate process. Loop till powergate START bit is asserted. |
| 71 | */ |
| 72 | do { |
| 73 | val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); |
| 74 | } while (val & (1 << 8)); |
| 75 | |
| 76 | /* loop till the CPU is power ungated */ |
| 77 | do { |
| 78 | val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); |
| 79 | } while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0); |
| 80 | } |
| 81 | |
| 82 | /******************************************************************************* |
| 83 | * Setup CPU vectors for resume from deep sleep |
| 84 | ******************************************************************************/ |
| 85 | void tegra_pmc_cpu_setup(uint64_t reset_addr) |
| 86 | { |
| 87 | uint32_t val; |
| 88 | |
| 89 | tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1); |
| 90 | val = reset_addr >> 32; |
| 91 | tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF); |
| 92 | } |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * Lock CPU vectors to restrict further writes |
| 96 | ******************************************************************************/ |
| 97 | void tegra_pmc_lock_cpu_vectors(void) |
| 98 | { |
| 99 | uint32_t val; |
| 100 | |
| 101 | /* lock PMC_SECURE_SCRATCH34/35 */ |
| 102 | val = tegra_pmc_read_32(PMC_SECURE_DISABLE3); |
| 103 | val |= (PMC_SECURE_DISABLE3_WRITE34_ON | |
| 104 | PMC_SECURE_DISABLE3_WRITE35_ON); |
| 105 | tegra_pmc_write_32(PMC_SECURE_DISABLE3, val); |
| 106 | } |
| 107 | |
| 108 | /******************************************************************************* |
| 109 | * Restart the system |
| 110 | ******************************************************************************/ |
| 111 | __dead2 void tegra_pmc_system_reset(void) |
| 112 | { |
| 113 | uint32_t reg; |
| 114 | |
| 115 | reg = tegra_pmc_read_32(PMC_CONFIG); |
| 116 | reg |= 0x10; /* restart */ |
| 117 | tegra_pmc_write_32(PMC_CONFIG, reg); |
| 118 | wfi(); |
| 119 | |
| 120 | ERROR("Tegra System Reset: operation not handled.\n"); |
| 121 | panic(); |
| 122 | } |