Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <debug.h> |
| 34 | #include <mmio.h> |
| 35 | #include <pmc.h> |
| 36 | #include <cortex_a53.h> |
| 37 | #include <flowctrl.h> |
| 38 | #include <tegra_def.h> |
| 39 | |
| 40 | #define CLK_RST_DEV_L_SET 0x300 |
| 41 | #define CLK_RST_DEV_L_CLR 0x304 |
| 42 | #define CLK_BPMP_RST (1 << 1) |
| 43 | |
| 44 | #define EVP_BPMP_RESET_VECTOR 0x200 |
| 45 | |
| 46 | static const uint64_t flowctrl_offset_cpu_csr[4] = { |
| 47 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR), |
| 48 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR), |
| 49 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8), |
| 50 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16) |
| 51 | }; |
| 52 | |
| 53 | static const uint64_t flowctrl_offset_halt_cpu[4] = { |
| 54 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS), |
| 55 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS), |
| 56 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8), |
| 57 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16) |
| 58 | }; |
| 59 | |
| 60 | static const uint64_t flowctrl_offset_cc4_ctrl[4] = { |
| 61 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL), |
| 62 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4), |
| 63 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8), |
| 64 | (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12) |
| 65 | }; |
| 66 | |
| 67 | static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) |
| 68 | { |
| 69 | mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); |
| 70 | val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); |
| 71 | } |
| 72 | |
| 73 | static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) |
| 74 | { |
| 75 | mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); |
| 76 | val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); |
| 77 | } |
| 78 | |
| 79 | static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) |
| 80 | { |
| 81 | mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); |
| 82 | val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); |
| 83 | } |
| 84 | |
| 85 | static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) |
| 86 | { |
| 87 | uint32_t val; |
| 88 | |
| 89 | val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ | |
| 90 | FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ | |
| 91 | FLOWCTRL_WAITEVENT; |
| 92 | tegra_fc_halt_cpu(cpu_id, val); |
| 93 | |
| 94 | val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | |
| 95 | FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id); |
| 96 | tegra_fc_cpu_csr(cpu_id, val | csr); |
| 97 | } |
| 98 | |
| 99 | /******************************************************************************* |
| 100 | * Suspend the current CPU |
| 101 | ******************************************************************************/ |
| 102 | void tegra_fc_cpu_idle(uint32_t mpidr) |
| 103 | { |
| 104 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 105 | |
| 106 | VERBOSE("CPU%d powering down...\n", cpu); |
| 107 | tegra_fc_prepare_suspend(cpu, 0); |
| 108 | } |
| 109 | |
| 110 | /******************************************************************************* |
| 111 | * Suspend the current CPU cluster |
| 112 | ******************************************************************************/ |
| 113 | void tegra_fc_cluster_idle(uint32_t mpidr) |
| 114 | { |
| 115 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 116 | uint32_t val; |
| 117 | |
| 118 | VERBOSE("Entering cluster idle state...\n"); |
| 119 | |
| 120 | tegra_fc_cc4_ctrl(cpu, 0); |
| 121 | |
| 122 | /* hardware L2 flush is faster for A53 only */ |
| 123 | tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, |
| 124 | !!MPIDR_AFFLVL1_VAL(mpidr)); |
| 125 | |
| 126 | /* suspend the CPU cluster */ |
| 127 | val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT; |
| 128 | tegra_fc_prepare_suspend(cpu, val); |
| 129 | } |
| 130 | |
| 131 | /******************************************************************************* |
| 132 | * Power down the current CPU cluster |
| 133 | ******************************************************************************/ |
| 134 | void tegra_fc_cluster_powerdn(uint32_t mpidr) |
| 135 | { |
| 136 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 137 | uint32_t val; |
| 138 | |
| 139 | VERBOSE("Entering cluster powerdn state...\n"); |
| 140 | |
| 141 | tegra_fc_cc4_ctrl(cpu, 0); |
| 142 | |
| 143 | /* hardware L2 flush is faster for A53 only */ |
| 144 | tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, |
| 145 | read_midr() == CORTEX_A53_MIDR); |
| 146 | |
| 147 | /* power down the CPU cluster */ |
| 148 | val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; |
| 149 | tegra_fc_prepare_suspend(cpu, val); |
| 150 | } |
| 151 | |
| 152 | /******************************************************************************* |
| 153 | * Suspend the entire SoC |
| 154 | ******************************************************************************/ |
| 155 | void tegra_fc_soc_powerdn(uint32_t mpidr) |
| 156 | { |
| 157 | int cpu = mpidr & MPIDR_CPU_MASK; |
| 158 | uint32_t val; |
| 159 | |
| 160 | VERBOSE("Entering SoC powerdn state...\n"); |
| 161 | |
| 162 | tegra_fc_cc4_ctrl(cpu, 0); |
| 163 | |
| 164 | tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1); |
| 165 | |
| 166 | val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; |
| 167 | tegra_fc_prepare_suspend(cpu, val); |
| 168 | |
| 169 | /* overwrite HALT register */ |
| 170 | tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); |
| 171 | } |
| 172 | |
| 173 | /******************************************************************************* |
| 174 | * Power up the CPU |
| 175 | ******************************************************************************/ |
| 176 | void tegra_fc_cpu_on(int cpu) |
| 177 | { |
| 178 | tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE); |
| 179 | tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK); |
| 180 | } |
| 181 | |
| 182 | /******************************************************************************* |
| 183 | * Power down the CPU |
| 184 | ******************************************************************************/ |
| 185 | void tegra_fc_cpu_off(int cpu) |
| 186 | { |
| 187 | uint32_t val; |
| 188 | |
| 189 | /* |
| 190 | * Flow controller powers down the CPU during wfi. The CPU would be |
| 191 | * powered on when it receives any interrupt. |
| 192 | */ |
| 193 | val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | |
| 194 | FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu); |
| 195 | tegra_fc_cpu_csr(cpu, val); |
| 196 | tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); |
| 197 | tegra_fc_cc4_ctrl(cpu, 0); |
| 198 | } |
| 199 | |
| 200 | /******************************************************************************* |
| 201 | * Inform the BPMP that we have completed the cluster power up |
| 202 | ******************************************************************************/ |
| 203 | void tegra_fc_lock_active_cluster(void) |
| 204 | { |
| 205 | uint32_t val; |
| 206 | |
| 207 | val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); |
| 208 | val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK; |
| 209 | tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val); |
| 210 | val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); |
| 211 | } |
| 212 | |
| 213 | /******************************************************************************* |
| 214 | * Reset BPMP processor |
| 215 | ******************************************************************************/ |
| 216 | void tegra_fc_reset_bpmp(void) |
| 217 | { |
| 218 | uint32_t val; |
| 219 | |
| 220 | /* halt BPMP */ |
| 221 | tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); |
| 222 | |
| 223 | /* Assert BPMP reset */ |
| 224 | mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); |
| 225 | |
| 226 | /* Restore reset address (stored in PMC_SCRATCH39) */ |
| 227 | val = tegra_pmc_read_32(PMC_SCRATCH39); |
| 228 | mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, val); |
| 229 | while (val != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) |
| 230 | ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ |
| 231 | |
| 232 | /* Wait for 2us before de-asserting the reset signal. */ |
| 233 | val = mmio_read_32(TEGRA_TMRUS_BASE); |
| 234 | val += 2; |
| 235 | while (val > mmio_read_32(TEGRA_TMRUS_BASE)) |
| 236 | ; /* wait for 2us */ |
| 237 | |
| 238 | /* De-assert BPMP reset */ |
| 239 | mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST); |
| 240 | |
| 241 | /* Un-halt BPMP */ |
| 242 | tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0); |
| 243 | } |