blob: 5aa5497777e2c71fc8396470da1e371ff01506c1 [file] [log] [blame]
Jiafei Pan46367ad2018-03-02 07:23:30 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <drivers/console.h>
Jiafei Pan46367ad2018-03-02 07:23:30 +00009#include <platform_def.h>
10
11 .weak plat_my_core_pos
12 .globl plat_crash_console_init
13 .globl plat_crash_console_putc
14 .globl plat_crash_console_flush
15 .weak platform_mem_init
16 .globl plat_ls_calc_core_pos
17
18
19 /* -----------------------------------------------------
20 * unsigned int plat_my_core_pos(void)
21 * This function uses the plat_ls_calc_core_pos()
22 * definition to get the index of the calling CPU.
23 * -----------------------------------------------------
24 */
25func plat_my_core_pos
26 mrs x0, mpidr_el1
27 b plat_ls_calc_core_pos
28endfunc plat_my_core_pos
29
30 /* -----------------------------------------------------
31 * unsigned int plat_ls_calc_core_pos(u_register_t mpidr)
32 * Helper function to calculate the core position.
33 * With this function: CorePos = (ClusterId * 4) +
34 * CoreId
35 * -----------------------------------------------------
36 */
37func plat_ls_calc_core_pos
38 and x1, x0, #MPIDR_CPU_MASK
39 and x0, x0, #MPIDR_CLUSTER_MASK
40 add x0, x1, x0, LSR #6
41 ret
42endfunc plat_ls_calc_core_pos
43
44 /* ---------------------------------------------
45 * int plat_crash_console_init(void)
46 * Function to initialize the crash console
47 * without a C Runtime to print crash report.
48 * Clobber list : x0 - x4
49 * ---------------------------------------------
50 */
51
Jiafei Pan46367ad2018-03-02 07:23:30 +000052 /* -----------------------------------------------------
53 * int plat_crash_console_init(void)
54 * Use normal console by default. Switch it to crash
55 * mode so serial consoles become active again.
56 * NOTE: This default implementation will only work for
57 * crashes that occur after a normal console (marked
58 * valid for the crash state) has been registered with
59 * the console framework. To debug crashes that occur
60 * earlier, the platform has to override these functions
61 * with an implementation that initializes a console
62 * driver with hardcoded parameters. See
63 * docs/porting-guide.rst for more information.
64 * -----------------------------------------------------
65 */
66func plat_crash_console_init
67#if defined(IMAGE_BL1)
68 /*
69 * BL1 code can possibly crash so early that the data segment is not yet
70 * accessible. Don't risk undefined behavior by trying to run the normal
71 * console framework. Platforms that want to debug BL1 will need to
72 * override this with custom functions that can run from registers only.
73 */
74 mov x0, #0
75 ret
76#else /* IMAGE_BL1 */
77 mov x3, x30
78 mov x0, #CONSOLE_FLAG_CRASH
79 bl console_switch_state
80 mov x0, #1
81 ret x3
82#endif
83endfunc plat_crash_console_init
84
85 /* -----------------------------------------------------
86 * void plat_crash_console_putc(int character)
87 * Output through the normal console by default.
88 * -----------------------------------------------------
89 */
90func plat_crash_console_putc
91 b console_putc
92endfunc plat_crash_console_putc
93
94 /* -----------------------------------------------------
95 * void plat_crash_console_flush(void)
96 * Flush normal console by default.
97 * -----------------------------------------------------
98 */
99func plat_crash_console_flush
100 b console_flush
101endfunc plat_crash_console_flush
102
Jiafei Pan46367ad2018-03-02 07:23:30 +0000103 /* ---------------------------------------------------------------------
104 * We don't need to carry out any memory initialization on LS
105 * platforms. The Secure SRAM is accessible straight away.
106 * ---------------------------------------------------------------------
107 */
108func platform_mem_init
109 ret
110endfunc platform_mem_init