Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 1 | /* |
John Powell | a5c6636 | 2020-03-20 14:21:05 -0500 | [diff] [blame] | 2 | * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef ARCH_H |
| 8 | #define ARCH_H |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 11 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 12 | /******************************************************************************* |
| 13 | * MIDR bit definitions |
| 14 | ******************************************************************************/ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 15 | #define MIDR_IMPL_MASK U(0xff) |
| 16 | #define MIDR_IMPL_SHIFT U(24) |
| 17 | #define MIDR_VAR_SHIFT U(20) |
| 18 | #define MIDR_VAR_BITS U(4) |
| 19 | #define MIDR_REV_SHIFT U(0) |
| 20 | #define MIDR_REV_BITS U(4) |
| 21 | #define MIDR_PN_MASK U(0xfff) |
| 22 | #define MIDR_PN_SHIFT U(4) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 23 | |
| 24 | /******************************************************************************* |
| 25 | * MPIDR macros |
| 26 | ******************************************************************************/ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 27 | #define MPIDR_MT_MASK (U(1) << 24) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 28 | #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
| 29 | #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 30 | #define MPIDR_AFFINITY_BITS U(8) |
| 31 | #define MPIDR_AFFLVL_MASK U(0xff) |
| 32 | #define MPIDR_AFFLVL_SHIFT U(3) |
| 33 | #define MPIDR_AFF0_SHIFT U(0) |
| 34 | #define MPIDR_AFF1_SHIFT U(8) |
| 35 | #define MPIDR_AFF2_SHIFT U(16) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 36 | #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 37 | #define MPIDR_AFFINITY_MASK U(0x00ffffff) |
| 38 | #define MPIDR_AFFLVL0 U(0) |
| 39 | #define MPIDR_AFFLVL1 U(1) |
| 40 | #define MPIDR_AFFLVL2 U(2) |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 41 | #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 42 | |
| 43 | #define MPIDR_AFFLVL0_VAL(mpidr) \ |
| 44 | (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) |
| 45 | #define MPIDR_AFFLVL1_VAL(mpidr) \ |
| 46 | (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) |
| 47 | #define MPIDR_AFFLVL2_VAL(mpidr) \ |
| 48 | (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 49 | #define MPIDR_AFFLVL3_VAL(mpidr) U(0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 50 | |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 51 | #define MPIDR_AFF_ID(mpid, n) \ |
| 52 | (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) |
| 53 | |
| 54 | #define MPID_MASK (MPIDR_MT_MASK |\ |
| 55 | (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ |
| 56 | (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ |
| 57 | (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) |
| 58 | |
| 59 | /* |
| 60 | * An invalid MPID. This value can be used by functions that return an MPID to |
| 61 | * indicate an error. |
| 62 | */ |
| 63 | #define INVALID_MPID U(0xFFFFFFFF) |
| 64 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 65 | /* |
| 66 | * The MPIDR_MAX_AFFLVL count starts from 0. Take care to |
| 67 | * add one while using this macro to define array sizes. |
| 68 | */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 69 | #define MPIDR_MAX_AFFLVL U(2) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 70 | |
| 71 | /* Data Cache set/way op type defines */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 72 | #define DC_OP_ISW U(0x0) |
| 73 | #define DC_OP_CISW U(0x1) |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 74 | #if ERRATA_A53_827319 |
| 75 | #define DC_OP_CSW DC_OP_CISW |
| 76 | #else |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 77 | #define DC_OP_CSW U(0x2) |
Ambroise Vincent | f5fdfbc | 2019-02-21 14:16:24 +0000 | [diff] [blame] | 78 | #endif |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 79 | |
| 80 | /******************************************************************************* |
| 81 | * Generic timer memory mapped registers & offsets |
| 82 | ******************************************************************************/ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 83 | #define CNTCR_OFF U(0x000) |
Yann Gautier | 007d745 | 2019-04-17 13:47:07 +0200 | [diff] [blame] | 84 | /* Counter Count Value Lower register */ |
| 85 | #define CNTCVL_OFF U(0x008) |
| 86 | /* Counter Count Value Upper register */ |
| 87 | #define CNTCVU_OFF U(0x00C) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 88 | #define CNTFID_OFF U(0x020) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 89 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 90 | #define CNTCR_EN (U(1) << 0) |
| 91 | #define CNTCR_HDBG (U(1) << 1) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 92 | #define CNTCR_FCREQ(x) ((x) << 8) |
| 93 | |
| 94 | /******************************************************************************* |
| 95 | * System register bit definitions |
| 96 | ******************************************************************************/ |
| 97 | /* CLIDR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 98 | #define LOUIS_SHIFT U(21) |
| 99 | #define LOC_SHIFT U(24) |
| 100 | #define CLIDR_FIELD_WIDTH U(3) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 101 | |
| 102 | /* CSSELR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 103 | #define LEVEL_SHIFT U(1) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 104 | |
Javier Almansa Sobrino | f3a4c54 | 2020-11-23 18:38:15 +0000 | [diff] [blame] | 105 | /* ID_DFR1_EL1 definitions */ |
| 106 | #define ID_DFR1_MTPMU_SHIFT U(0) |
| 107 | #define ID_DFR1_MTPMU_MASK U(0xf) |
| 108 | #define ID_DFR1_MTPMU_SUPPORTED U(1) |
| 109 | |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 110 | /* ID_MMFR4 definitions */ |
| 111 | #define ID_MMFR4_CNP_SHIFT U(12) |
| 112 | #define ID_MMFR4_CNP_LENGTH U(4) |
| 113 | #define ID_MMFR4_CNP_MASK U(0xf) |
| 114 | |
| 115 | /* ID_PFR0 definitions */ |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 116 | #define ID_PFR0_AMU_SHIFT U(20) |
| 117 | #define ID_PFR0_AMU_LENGTH U(4) |
| 118 | #define ID_PFR0_AMU_MASK U(0xf) |
| 119 | |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 120 | #define ID_PFR0_DIT_SHIFT U(24) |
| 121 | #define ID_PFR0_DIT_LENGTH U(4) |
| 122 | #define ID_PFR0_DIT_MASK U(0xf) |
| 123 | #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) |
| 124 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 125 | /* ID_PFR1 definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 126 | #define ID_PFR1_VIRTEXT_SHIFT U(12) |
| 127 | #define ID_PFR1_VIRTEXT_MASK U(0xf) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 128 | #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ |
| 129 | & ID_PFR1_VIRTEXT_MASK) |
Antonio Nino Diaz | d29d21e | 2019-02-06 09:23:04 +0000 | [diff] [blame] | 130 | #define ID_PFR1_GENTIMER_SHIFT U(16) |
| 131 | #define ID_PFR1_GENTIMER_MASK U(0xf) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 132 | #define ID_PFR1_GIC_SHIFT U(28) |
| 133 | #define ID_PFR1_GIC_MASK U(0xf) |
Javier Almansa Sobrino | f3a4c54 | 2020-11-23 18:38:15 +0000 | [diff] [blame] | 134 | #define ID_PFR1_SEC_SHIFT U(4) |
| 135 | #define ID_PFR1_SEC_MASK U(0xf) |
| 136 | #define ID_PFR1_ELx_ENABLED U(1) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 137 | |
| 138 | /* SCTLR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 139 | #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ |
| 140 | (U(1) << 3)) |
Etienne Carriere | 70a004b | 2017-11-05 22:56:03 +0100 | [diff] [blame] | 141 | #if ARM_ARCH_MAJOR == 7 |
| 142 | #define SCTLR_RES1 SCTLR_RES1_DEF |
| 143 | #else |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 144 | #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) |
Etienne Carriere | 70a004b | 2017-11-05 22:56:03 +0100 | [diff] [blame] | 145 | #endif |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 146 | #define SCTLR_M_BIT (U(1) << 0) |
| 147 | #define SCTLR_A_BIT (U(1) << 1) |
| 148 | #define SCTLR_C_BIT (U(1) << 2) |
| 149 | #define SCTLR_CP15BEN_BIT (U(1) << 5) |
| 150 | #define SCTLR_ITD_BIT (U(1) << 7) |
| 151 | #define SCTLR_Z_BIT (U(1) << 11) |
| 152 | #define SCTLR_I_BIT (U(1) << 12) |
| 153 | #define SCTLR_V_BIT (U(1) << 13) |
| 154 | #define SCTLR_RR_BIT (U(1) << 14) |
| 155 | #define SCTLR_NTWI_BIT (U(1) << 16) |
| 156 | #define SCTLR_NTWE_BIT (U(1) << 18) |
| 157 | #define SCTLR_WXN_BIT (U(1) << 19) |
| 158 | #define SCTLR_UWXN_BIT (U(1) << 20) |
| 159 | #define SCTLR_EE_BIT (U(1) << 25) |
| 160 | #define SCTLR_TRE_BIT (U(1) << 28) |
| 161 | #define SCTLR_AFE_BIT (U(1) << 29) |
| 162 | #define SCTLR_TE_BIT (U(1) << 30) |
Jeenu Viswambharan | aa00aff | 2018-11-15 11:38:03 +0000 | [diff] [blame] | 163 | #define SCTLR_DSSBS_BIT (U(1) << 31) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 164 | #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ |
| 165 | SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 166 | |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 167 | /* SDCR definitions */ |
| 168 | #define SDCR_SPD(x) ((x) << 14) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 169 | #define SDCR_SPD_LEGACY U(0x0) |
| 170 | #define SDCR_SPD_DISABLE U(0x2) |
| 171 | #define SDCR_SPD_ENABLE U(0x3) |
Antonio Nino Diaz | 3fbd3f5 | 2019-02-18 16:55:43 +0000 | [diff] [blame] | 172 | #define SDCR_SCCD_BIT (U(1) << 23) |
Alexei Fedorov | 9074dea | 2019-08-20 15:22:44 +0100 | [diff] [blame] | 173 | #define SDCR_SPME_BIT (U(1) << 17) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 174 | #define SDCR_RESET_VAL U(0x0) |
Javier Almansa Sobrino | f3a4c54 | 2020-11-23 18:38:15 +0000 | [diff] [blame] | 175 | #define SDCR_MTPME_BIT (U(1) << 28) |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 176 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 177 | /* HSCTLR definitions */ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 178 | #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 179 | (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ |
| 180 | (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) |
| 181 | |
| 182 | #define HSCTLR_M_BIT (U(1) << 0) |
| 183 | #define HSCTLR_A_BIT (U(1) << 1) |
| 184 | #define HSCTLR_C_BIT (U(1) << 2) |
| 185 | #define HSCTLR_CP15BEN_BIT (U(1) << 5) |
| 186 | #define HSCTLR_ITD_BIT (U(1) << 7) |
| 187 | #define HSCTLR_SED_BIT (U(1) << 8) |
| 188 | #define HSCTLR_I_BIT (U(1) << 12) |
| 189 | #define HSCTLR_WXN_BIT (U(1) << 19) |
| 190 | #define HSCTLR_EE_BIT (U(1) << 25) |
| 191 | #define HSCTLR_TE_BIT (U(1) << 30) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 192 | |
| 193 | /* CPACR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 194 | #define CPACR_FPEN(x) ((x) << 20) |
Jimmy Brisson | ed20207 | 2020-08-04 16:18:52 -0500 | [diff] [blame] | 195 | #define CPACR_FP_TRAP_PL0 UL(0x1) |
| 196 | #define CPACR_FP_TRAP_ALL UL(0x2) |
| 197 | #define CPACR_FP_TRAP_NONE UL(0x3) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 198 | |
| 199 | /* SCR definitions */ |
Jimmy Brisson | ed20207 | 2020-08-04 16:18:52 -0500 | [diff] [blame] | 200 | #define SCR_TWE_BIT (UL(1) << 13) |
| 201 | #define SCR_TWI_BIT (UL(1) << 12) |
| 202 | #define SCR_SIF_BIT (UL(1) << 9) |
| 203 | #define SCR_HCE_BIT (UL(1) << 8) |
| 204 | #define SCR_SCD_BIT (UL(1) << 7) |
| 205 | #define SCR_NET_BIT (UL(1) << 6) |
| 206 | #define SCR_AW_BIT (UL(1) << 5) |
| 207 | #define SCR_FW_BIT (UL(1) << 4) |
| 208 | #define SCR_EA_BIT (UL(1) << 3) |
| 209 | #define SCR_FIQ_BIT (UL(1) << 2) |
| 210 | #define SCR_IRQ_BIT (UL(1) << 1) |
| 211 | #define SCR_NS_BIT (UL(1) << 0) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 212 | #define SCR_VALID_BIT_MASK U(0x33ff) |
| 213 | #define SCR_RESET_VAL U(0x0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 214 | |
| 215 | #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) |
| 216 | |
| 217 | /* HCR definitions */ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 218 | #define HCR_TGE_BIT (U(1) << 27) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 219 | #define HCR_AMO_BIT (U(1) << 5) |
| 220 | #define HCR_IMO_BIT (U(1) << 4) |
| 221 | #define HCR_FMO_BIT (U(1) << 3) |
| 222 | #define HCR_RESET_VAL U(0x0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 223 | |
| 224 | /* CNTHCTL definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 225 | #define CNTHCTL_RESET_VAL U(0x0) |
| 226 | #define PL1PCEN_BIT (U(1) << 1) |
| 227 | #define PL1PCTEN_BIT (U(1) << 0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 228 | |
| 229 | /* CNTKCTL definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 230 | #define PL0PTEN_BIT (U(1) << 9) |
| 231 | #define PL0VTEN_BIT (U(1) << 8) |
| 232 | #define PL0PCTEN_BIT (U(1) << 0) |
| 233 | #define PL0VCTEN_BIT (U(1) << 1) |
| 234 | #define EVNTEN_BIT (U(1) << 2) |
| 235 | #define EVNTDIR_BIT (U(1) << 3) |
| 236 | #define EVNTI_SHIFT U(4) |
| 237 | #define EVNTI_MASK U(0xf) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 238 | |
| 239 | /* HCPTR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 240 | #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) |
| 241 | #define TCPAC_BIT (U(1) << 31) |
| 242 | #define TAM_BIT (U(1) << 30) |
| 243 | #define TTA_BIT (U(1) << 20) |
Sandrine Bailleux | 6061c45 | 2018-07-13 10:04:12 +0200 | [diff] [blame] | 244 | #define TCP11_BIT (U(1) << 11) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 245 | #define TCP10_BIT (U(1) << 10) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 246 | #define HCPTR_RESET_VAL HCPTR_RES1 |
| 247 | |
| 248 | /* VTTBR defintions */ |
| 249 | #define VTTBR_RESET_VAL ULL(0x0) |
| 250 | #define VTTBR_VMID_MASK ULL(0xff) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 251 | #define VTTBR_VMID_SHIFT U(48) |
| 252 | #define VTTBR_BADDR_MASK ULL(0xffffffffffff) |
| 253 | #define VTTBR_BADDR_SHIFT U(0) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 254 | |
| 255 | /* HDCR definitions */ |
Javier Almansa Sobrino | f3a4c54 | 2020-11-23 18:38:15 +0000 | [diff] [blame] | 256 | #define HDCR_MTPME_BIT (U(1) << 28) |
Alexei Fedorov | 9074dea | 2019-08-20 15:22:44 +0100 | [diff] [blame] | 257 | #define HDCR_HLP_BIT (U(1) << 26) |
| 258 | #define HDCR_HPME_BIT (U(1) << 7) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 259 | #define HDCR_RESET_VAL U(0x0) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 260 | |
| 261 | /* HSTR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 262 | #define HSTR_RESET_VAL U(0x0) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 263 | |
| 264 | /* CNTHP_CTL definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 265 | #define CNTHP_CTL_RESET_VAL U(0x0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 266 | |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 267 | /* NSACR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 268 | #define NSASEDIS_BIT (U(1) << 15) |
| 269 | #define NSTRCDIS_BIT (U(1) << 20) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 270 | #define NSACR_CP11_BIT (U(1) << 11) |
| 271 | #define NSACR_CP10_BIT (U(1) << 10) |
| 272 | #define NSACR_IMP_DEF_MASK (U(0x7) << 16) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 273 | #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 274 | #define NSACR_RESET_VAL U(0x0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 275 | |
| 276 | /* CPACR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 277 | #define ASEDIS_BIT (U(1) << 31) |
| 278 | #define TRCDIS_BIT (U(1) << 28) |
| 279 | #define CPACR_CP11_SHIFT U(22) |
| 280 | #define CPACR_CP10_SHIFT U(20) |
| 281 | #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ |
| 282 | (U(0x3) << CPACR_CP10_SHIFT)) |
| 283 | #define CPACR_RESET_VAL U(0x0) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 284 | |
| 285 | /* FPEXC definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 286 | #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) |
| 287 | #define FPEXC_EN_BIT (U(1) << 30) |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 288 | #define FPEXC_RESET_VAL FPEXC_RES1 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 289 | |
| 290 | /* SPSR/CPSR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 291 | #define SPSR_FIQ_BIT (U(1) << 0) |
| 292 | #define SPSR_IRQ_BIT (U(1) << 1) |
| 293 | #define SPSR_ABT_BIT (U(1) << 2) |
| 294 | #define SPSR_AIF_SHIFT U(6) |
| 295 | #define SPSR_AIF_MASK U(0x7) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 296 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 297 | #define SPSR_E_SHIFT U(9) |
| 298 | #define SPSR_E_MASK U(0x1) |
| 299 | #define SPSR_E_LITTLE U(0) |
| 300 | #define SPSR_E_BIG U(1) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 301 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 302 | #define SPSR_T_SHIFT U(5) |
| 303 | #define SPSR_T_MASK U(0x1) |
| 304 | #define SPSR_T_ARM U(0) |
| 305 | #define SPSR_T_THUMB U(1) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 306 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 307 | #define SPSR_MODE_SHIFT U(0) |
| 308 | #define SPSR_MODE_MASK U(0x7) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 309 | |
John Tsichritzis | 5553417 | 2019-07-23 11:12:41 +0100 | [diff] [blame] | 310 | #define SPSR_SSBS_BIT BIT_32(23) |
| 311 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 312 | #define DISABLE_ALL_EXCEPTIONS \ |
| 313 | (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) |
| 314 | |
Sathees Balya | 0911df1 | 2018-12-06 13:33:24 +0000 | [diff] [blame] | 315 | #define CPSR_DIT_BIT (U(1) << 21) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 316 | /* |
| 317 | * TTBCR definitions |
| 318 | */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 319 | #define TTBCR_EAE_BIT (U(1) << 31) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 320 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 321 | #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) |
| 322 | #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) |
| 323 | #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 324 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 325 | #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) |
| 326 | #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) |
| 327 | #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) |
| 328 | #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 329 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 330 | #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) |
| 331 | #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) |
| 332 | #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) |
| 333 | #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 334 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 335 | #define TTBCR_EPD1_BIT (U(1) << 23) |
| 336 | #define TTBCR_A1_BIT (U(1) << 22) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 337 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 338 | #define TTBCR_T1SZ_SHIFT U(16) |
| 339 | #define TTBCR_T1SZ_MASK U(0x7) |
| 340 | #define TTBCR_TxSZ_MIN U(0) |
| 341 | #define TTBCR_TxSZ_MAX U(7) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 342 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 343 | #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) |
| 344 | #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) |
| 345 | #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 346 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 347 | #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) |
| 348 | #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) |
| 349 | #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) |
| 350 | #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 351 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 352 | #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) |
| 353 | #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) |
| 354 | #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) |
| 355 | #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 356 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 357 | #define TTBCR_EPD0_BIT (U(1) << 7) |
| 358 | #define TTBCR_T0SZ_SHIFT U(0) |
| 359 | #define TTBCR_T0SZ_MASK U(0x7) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 360 | |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 361 | /* |
| 362 | * HTCR definitions |
| 363 | */ |
| 364 | #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) |
| 365 | |
| 366 | #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) |
| 367 | #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) |
| 368 | #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) |
| 369 | |
| 370 | #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) |
| 371 | #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) |
| 372 | #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) |
| 373 | #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) |
| 374 | |
| 375 | #define HTCR_RGN0_INNER_NC (U(0x0) << 8) |
| 376 | #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) |
| 377 | #define HTCR_RGN0_INNER_WT (U(0x2) << 8) |
| 378 | #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) |
| 379 | |
| 380 | #define HTCR_T0SZ_SHIFT U(0) |
| 381 | #define HTCR_T0SZ_MASK U(0x7) |
| 382 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 383 | #define MODE_RW_SHIFT U(0x4) |
| 384 | #define MODE_RW_MASK U(0x1) |
| 385 | #define MODE_RW_32 U(0x1) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 386 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 387 | #define MODE32_SHIFT U(0) |
| 388 | #define MODE32_MASK U(0x1f) |
| 389 | #define MODE32_usr U(0x10) |
| 390 | #define MODE32_fiq U(0x11) |
| 391 | #define MODE32_irq U(0x12) |
| 392 | #define MODE32_svc U(0x13) |
| 393 | #define MODE32_mon U(0x16) |
| 394 | #define MODE32_abt U(0x17) |
| 395 | #define MODE32_hyp U(0x1a) |
| 396 | #define MODE32_und U(0x1b) |
| 397 | #define MODE32_sys U(0x1f) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 398 | |
| 399 | #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) |
| 400 | |
John Powell | a5c6636 | 2020-03-20 14:21:05 -0500 | [diff] [blame] | 401 | #define SPSR_MODE32(mode, isa, endian, aif) \ |
| 402 | ( \ |
| 403 | ( \ |
| 404 | (MODE_RW_32 << MODE_RW_SHIFT) | \ |
| 405 | (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ |
| 406 | (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ |
| 407 | (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ |
| 408 | (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ |
| 409 | ) & \ |
| 410 | (~(SPSR_SSBS_BIT)) \ |
| 411 | ) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 412 | |
| 413 | /* |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 414 | * TTBR definitions |
| 415 | */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 416 | #define TTBR_CNP_BIT ULL(0x1) |
Isla Mitchell | c4a1a07 | 2017-08-07 11:20:13 +0100 | [diff] [blame] | 417 | |
| 418 | /* |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 419 | * CTR definitions |
| 420 | */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 421 | #define CTR_CWG_SHIFT U(24) |
| 422 | #define CTR_CWG_MASK U(0xf) |
| 423 | #define CTR_ERG_SHIFT U(20) |
| 424 | #define CTR_ERG_MASK U(0xf) |
| 425 | #define CTR_DMINLINE_SHIFT U(16) |
| 426 | #define CTR_DMINLINE_WIDTH U(4) |
| 427 | #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) |
| 428 | #define CTR_L1IP_SHIFT U(14) |
| 429 | #define CTR_L1IP_MASK U(0x3) |
| 430 | #define CTR_IMINLINE_SHIFT U(0) |
| 431 | #define CTR_IMINLINE_MASK U(0xf) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 432 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 433 | #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 434 | |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 435 | /* PMCR definitions */ |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 436 | #define PMCR_N_SHIFT U(11) |
| 437 | #define PMCR_N_MASK U(0x1f) |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 438 | #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) |
Alexei Fedorov | 9074dea | 2019-08-20 15:22:44 +0100 | [diff] [blame] | 439 | #define PMCR_LP_BIT (U(1) << 7) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 440 | #define PMCR_LC_BIT (U(1) << 6) |
| 441 | #define PMCR_DP_BIT (U(1) << 5) |
Alexei Fedorov | 9074dea | 2019-08-20 15:22:44 +0100 | [diff] [blame] | 442 | #define PMCR_RESET_VAL U(0x0) |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 443 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 444 | /******************************************************************************* |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 445 | * Definitions of register offsets, fields and macros for CPU system |
| 446 | * instructions. |
| 447 | ******************************************************************************/ |
| 448 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 449 | #define TLBI_ADDR_SHIFT U(0) |
| 450 | #define TLBI_ADDR_MASK U(0xFFFFF000) |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 451 | #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) |
| 452 | |
| 453 | /******************************************************************************* |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 454 | * Definitions of register offsets and fields in the CNTCTLBase Frame of the |
| 455 | * system level implementation of the Generic Timer. |
| 456 | ******************************************************************************/ |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 457 | #define CNTCTLBASE_CNTFRQ U(0x0) |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 458 | #define CNTNSAR U(0x4) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 459 | #define CNTNSAR_NS_SHIFT(x) (x) |
| 460 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 461 | #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) |
| 462 | #define CNTACR_RPCT_SHIFT U(0x0) |
| 463 | #define CNTACR_RVCT_SHIFT U(0x1) |
| 464 | #define CNTACR_RFRQ_SHIFT U(0x2) |
| 465 | #define CNTACR_RVOFF_SHIFT U(0x3) |
| 466 | #define CNTACR_RWVT_SHIFT U(0x4) |
| 467 | #define CNTACR_RWPT_SHIFT U(0x5) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 468 | |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 469 | /******************************************************************************* |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 470 | * Definitions of register offsets and fields in the CNTBaseN Frame of the |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 471 | * system level implementation of the Generic Timer. |
| 472 | ******************************************************************************/ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 473 | /* Physical Count register. */ |
| 474 | #define CNTPCT_LO U(0x0) |
| 475 | /* Counter Frequency register. */ |
| 476 | #define CNTBASEN_CNTFRQ U(0x10) |
| 477 | /* Physical Timer CompareValue register. */ |
| 478 | #define CNTP_CVAL_LO U(0x20) |
| 479 | /* Physical Timer Control register. */ |
| 480 | #define CNTP_CTL U(0x2c) |
| 481 | |
| 482 | /* Physical timer control register bit fields shifts and masks */ |
| 483 | #define CNTP_CTL_ENABLE_SHIFT 0 |
| 484 | #define CNTP_CTL_IMASK_SHIFT 1 |
| 485 | #define CNTP_CTL_ISTATUS_SHIFT 2 |
| 486 | |
| 487 | #define CNTP_CTL_ENABLE_MASK U(1) |
| 488 | #define CNTP_CTL_IMASK_MASK U(1) |
| 489 | #define CNTP_CTL_ISTATUS_MASK U(1) |
Soby Mathew | 2d9f795 | 2018-06-11 16:21:30 +0100 | [diff] [blame] | 490 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 491 | /* MAIR macros */ |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 492 | #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) |
| 493 | #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 494 | |
| 495 | /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ |
| 496 | #define SCR p15, 0, c1, c1, 0 |
| 497 | #define SCTLR p15, 0, c1, c0, 0 |
Etienne Carriere | 70a004b | 2017-11-05 22:56:03 +0100 | [diff] [blame] | 498 | #define ACTLR p15, 0, c1, c0, 1 |
dp-arm | 595d0d5 | 2017-02-08 11:51:50 +0000 | [diff] [blame] | 499 | #define SDCR p15, 0, c1, c3, 1 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 500 | #define MPIDR p15, 0, c0, c0, 5 |
| 501 | #define MIDR p15, 0, c0, c0, 0 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 502 | #define HVBAR p15, 4, c12, c0, 0 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 503 | #define VBAR p15, 0, c12, c0, 0 |
| 504 | #define MVBAR p15, 0, c12, c0, 1 |
| 505 | #define NSACR p15, 0, c1, c1, 2 |
| 506 | #define CPACR p15, 0, c1, c0, 2 |
| 507 | #define DCCIMVAC p15, 0, c7, c14, 1 |
| 508 | #define DCCMVAC p15, 0, c7, c10, 1 |
| 509 | #define DCIMVAC p15, 0, c7, c6, 1 |
| 510 | #define DCCISW p15, 0, c7, c14, 2 |
| 511 | #define DCCSW p15, 0, c7, c10, 2 |
| 512 | #define DCISW p15, 0, c7, c6, 2 |
| 513 | #define CTR p15, 0, c0, c0, 1 |
| 514 | #define CNTFRQ p15, 0, c14, c0, 0 |
Antonio Nino Diaz | c326c34 | 2019-01-11 11:20:10 +0000 | [diff] [blame] | 515 | #define ID_MMFR4 p15, 0, c0, c2, 6 |
Javier Almansa Sobrino | f3a4c54 | 2020-11-23 18:38:15 +0000 | [diff] [blame] | 516 | #define ID_DFR1 p15, 0, c0, c3, 5 |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 517 | #define ID_PFR0 p15, 0, c0, c1, 0 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 518 | #define ID_PFR1 p15, 0, c0, c1, 1 |
| 519 | #define MAIR0 p15, 0, c10, c2, 0 |
| 520 | #define MAIR1 p15, 0, c10, c2, 1 |
| 521 | #define TTBCR p15, 0, c2, c0, 2 |
| 522 | #define TTBR0 p15, 0, c2, c0, 0 |
| 523 | #define TTBR1 p15, 0, c2, c0, 1 |
| 524 | #define TLBIALL p15, 0, c8, c7, 0 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 525 | #define TLBIALLH p15, 4, c8, c7, 0 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 526 | #define TLBIALLIS p15, 0, c8, c3, 0 |
| 527 | #define TLBIMVA p15, 0, c8, c7, 1 |
| 528 | #define TLBIMVAA p15, 0, c8, c7, 3 |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 529 | #define TLBIMVAAIS p15, 0, c8, c3, 3 |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 530 | #define TLBIMVAHIS p15, 4, c8, c3, 1 |
Antonio Nino Diaz | ac99803 | 2017-02-27 17:23:54 +0000 | [diff] [blame] | 531 | #define BPIALLIS p15, 0, c7, c1, 6 |
Dimitris Papastamos | 0a4cded | 2018-01-02 11:37:02 +0000 | [diff] [blame] | 532 | #define BPIALL p15, 0, c7, c5, 6 |
| 533 | #define ICIALLU p15, 0, c7, c5, 0 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 534 | #define HSCTLR p15, 4, c1, c0, 0 |
| 535 | #define HCR p15, 4, c1, c1, 0 |
| 536 | #define HCPTR p15, 4, c1, c1, 2 |
David Cunado | fee8653 | 2017-04-13 22:38:29 +0100 | [diff] [blame] | 537 | #define HSTR p15, 4, c1, c1, 3 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 538 | #define CNTHCTL p15, 4, c14, c1, 0 |
Yatharth Kochar | 2694cba | 2016-11-14 12:00:41 +0000 | [diff] [blame] | 539 | #define CNTKCTL p15, 0, c14, c1, 0 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 540 | #define VPIDR p15, 4, c0, c0, 0 |
| 541 | #define VMPIDR p15, 4, c0, c0, 5 |
| 542 | #define ISR p15, 0, c12, c1, 0 |
| 543 | #define CLIDR p15, 1, c0, c0, 1 |
| 544 | #define CSSELR p15, 2, c0, c0, 0 |
| 545 | #define CCSIDR p15, 1, c0, c0, 0 |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 546 | #define HTCR p15, 4, c2, c0, 2 |
| 547 | #define HMAIR0 p15, 4, c10, c2, 0 |
Douglas Raillard | 7741463 | 2018-08-21 12:54:45 +0100 | [diff] [blame] | 548 | #define ATS1CPR p15, 0, c7, c8, 0 |
| 549 | #define ATS1HR p15, 4, c7, c8, 0 |
Yatharth Kochar | a9f776c | 2016-11-10 16:17:51 +0000 | [diff] [blame] | 550 | #define DBGOSDLR p14, 0, c1, c3, 4 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 551 | |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 552 | /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ |
| 553 | #define HDCR p15, 4, c1, c1, 1 |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 554 | #define PMCR p15, 0, c9, c12, 0 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 555 | #define CNTHP_TVAL p15, 4, c14, c2, 0 |
David Cunado | c14b08e | 2016-11-25 00:21:59 +0000 | [diff] [blame] | 556 | #define CNTHP_CTL p15, 4, c14, c2, 1 |
David Cunado | 5f55e28 | 2016-10-31 17:37:34 +0000 | [diff] [blame] | 557 | |
Etienne Carriere | 70a004b | 2017-11-05 22:56:03 +0100 | [diff] [blame] | 558 | /* AArch32 coproc registers for 32bit MMU descriptor support */ |
| 559 | #define PRRR p15, 0, c10, c2, 0 |
| 560 | #define NMRR p15, 0, c10, c2, 1 |
| 561 | #define DACR p15, 0, c3, c0, 0 |
| 562 | |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 563 | /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ |
| 564 | #define ICC_IAR1 p15, 0, c12, c12, 0 |
| 565 | #define ICC_IAR0 p15, 0, c12, c8, 0 |
| 566 | #define ICC_EOIR1 p15, 0, c12, c12, 1 |
| 567 | #define ICC_EOIR0 p15, 0, c12, c8, 1 |
| 568 | #define ICC_HPPIR1 p15, 0, c12, c12, 2 |
| 569 | #define ICC_HPPIR0 p15, 0, c12, c8, 2 |
| 570 | #define ICC_BPR1 p15, 0, c12, c12, 3 |
| 571 | #define ICC_BPR0 p15, 0, c12, c8, 3 |
| 572 | #define ICC_DIR p15, 0, c12, c11, 1 |
| 573 | #define ICC_PMR p15, 0, c4, c6, 0 |
| 574 | #define ICC_RPR p15, 0, c12, c11, 3 |
| 575 | #define ICC_CTLR p15, 0, c12, c12, 4 |
| 576 | #define ICC_MCTLR p15, 6, c12, c12, 4 |
| 577 | #define ICC_SRE p15, 0, c12, c12, 5 |
| 578 | #define ICC_HSRE p15, 4, c12, c9, 5 |
| 579 | #define ICC_MSRE p15, 6, c12, c12, 5 |
| 580 | #define ICC_IGRPEN0 p15, 0, c12, c12, 6 |
| 581 | #define ICC_IGRPEN1 p15, 0, c12, c12, 7 |
| 582 | #define ICC_MGRPEN1 p15, 6, c12, c12, 7 |
| 583 | |
| 584 | /* 64 bit system register defines The format is: coproc, opt1, CRm */ |
| 585 | #define TTBR0_64 p15, 0, c2 |
| 586 | #define TTBR1_64 p15, 1, c2 |
| 587 | #define CNTVOFF_64 p15, 4, c14 |
| 588 | #define VTTBR_64 p15, 6, c2 |
| 589 | #define CNTPCT_64 p15, 0, c14 |
Antonio Nino Diaz | 128de8d | 2018-08-07 19:59:49 +0100 | [diff] [blame] | 590 | #define HTTBR_64 p15, 4, c2 |
Antonio Nino Diaz | 8257f5b | 2018-11-22 15:53:17 +0000 | [diff] [blame] | 591 | #define CNTHP_CVAL_64 p15, 6, c14 |
Douglas Raillard | 7741463 | 2018-08-21 12:54:45 +0100 | [diff] [blame] | 592 | #define PAR_64 p15, 0, c7 |
Soby Mathew | c6820d1 | 2016-05-09 17:49:55 +0100 | [diff] [blame] | 593 | |
| 594 | /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ |
| 595 | #define ICC_SGI1R_EL1_64 p15, 0, c12 |
| 596 | #define ICC_ASGI1R_EL1_64 p15, 1, c12 |
| 597 | #define ICC_SGI0R_EL1_64 p15, 2, c12 |
| 598 | |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 599 | /******************************************************************************* |
| 600 | * Definitions of MAIR encodings for device and normal memory |
| 601 | ******************************************************************************/ |
| 602 | /* |
| 603 | * MAIR encodings for device memory attributes. |
| 604 | */ |
| 605 | #define MAIR_DEV_nGnRnE U(0x0) |
| 606 | #define MAIR_DEV_nGnRE U(0x4) |
| 607 | #define MAIR_DEV_nGRE U(0x8) |
| 608 | #define MAIR_DEV_GRE U(0xc) |
| 609 | |
| 610 | /* |
| 611 | * MAIR encodings for normal memory attributes. |
| 612 | * |
| 613 | * Cache Policy |
| 614 | * WT: Write Through |
| 615 | * WB: Write Back |
| 616 | * NC: Non-Cacheable |
| 617 | * |
| 618 | * Transient Hint |
| 619 | * NTR: Non-Transient |
| 620 | * TR: Transient |
| 621 | * |
| 622 | * Allocation Policy |
| 623 | * RA: Read Allocate |
| 624 | * WA: Write Allocate |
| 625 | * RWA: Read and Write Allocate |
| 626 | * NA: No Allocation |
| 627 | */ |
| 628 | #define MAIR_NORM_WT_TR_WA U(0x1) |
| 629 | #define MAIR_NORM_WT_TR_RA U(0x2) |
| 630 | #define MAIR_NORM_WT_TR_RWA U(0x3) |
| 631 | #define MAIR_NORM_NC U(0x4) |
| 632 | #define MAIR_NORM_WB_TR_WA U(0x5) |
| 633 | #define MAIR_NORM_WB_TR_RA U(0x6) |
| 634 | #define MAIR_NORM_WB_TR_RWA U(0x7) |
| 635 | #define MAIR_NORM_WT_NTR_NA U(0x8) |
| 636 | #define MAIR_NORM_WT_NTR_WA U(0x9) |
| 637 | #define MAIR_NORM_WT_NTR_RA U(0xa) |
| 638 | #define MAIR_NORM_WT_NTR_RWA U(0xb) |
| 639 | #define MAIR_NORM_WB_NTR_NA U(0xc) |
| 640 | #define MAIR_NORM_WB_NTR_WA U(0xd) |
| 641 | #define MAIR_NORM_WB_NTR_RA U(0xe) |
| 642 | #define MAIR_NORM_WB_NTR_RWA U(0xf) |
| 643 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 644 | #define MAIR_NORM_OUTER_SHIFT U(4) |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 645 | |
Antonio Nino Diaz | a3fbeaa | 2018-07-12 13:23:59 +0100 | [diff] [blame] | 646 | #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ |
| 647 | ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) |
Isla Mitchell | 02c6307 | 2017-07-21 14:44:36 +0100 | [diff] [blame] | 648 | |
Douglas Raillard | 7741463 | 2018-08-21 12:54:45 +0100 | [diff] [blame] | 649 | /* PAR fields */ |
| 650 | #define PAR_F_SHIFT U(0) |
| 651 | #define PAR_F_MASK ULL(0x1) |
| 652 | #define PAR_ADDR_SHIFT U(12) |
Yann Gautier | 812c325 | 2018-09-20 15:48:52 +0200 | [diff] [blame] | 653 | #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ |
Douglas Raillard | 7741463 | 2018-08-21 12:54:45 +0100 | [diff] [blame] | 654 | |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 655 | /******************************************************************************* |
| 656 | * Definitions for system register interface to AMU for ARMv8.4 onwards |
| 657 | ******************************************************************************/ |
| 658 | #define AMCR p15, 0, c13, c2, 0 |
| 659 | #define AMCFGR p15, 0, c13, c2, 1 |
| 660 | #define AMCGCR p15, 0, c13, c2, 2 |
| 661 | #define AMUSERENR p15, 0, c13, c2, 3 |
| 662 | #define AMCNTENCLR0 p15, 0, c13, c2, 4 |
| 663 | #define AMCNTENSET0 p15, 0, c13, c2, 5 |
| 664 | #define AMCNTENCLR1 p15, 0, c13, c3, 0 |
Joel Hutton | 0dcdd8d | 2017-12-21 15:21:20 +0000 | [diff] [blame] | 665 | #define AMCNTENSET1 p15, 0, c13, c3, 1 |
Dimitris Papastamos | dda48b0 | 2017-10-17 14:03:14 +0100 | [diff] [blame] | 666 | |
| 667 | /* Activity Monitor Group 0 Event Counter Registers */ |
| 668 | #define AMEVCNTR00 p15, 0, c0 |
| 669 | #define AMEVCNTR01 p15, 1, c0 |
| 670 | #define AMEVCNTR02 p15, 2, c0 |
| 671 | #define AMEVCNTR03 p15, 3, c0 |
| 672 | |
| 673 | /* Activity Monitor Group 0 Event Type Registers */ |
| 674 | #define AMEVTYPER00 p15, 0, c13, c6, 0 |
| 675 | #define AMEVTYPER01 p15, 0, c13, c6, 1 |
| 676 | #define AMEVTYPER02 p15, 0, c13, c6, 2 |
| 677 | #define AMEVTYPER03 p15, 0, c13, c6, 3 |
| 678 | |
Joel Hutton | 2691bc6 | 2017-12-12 15:47:55 +0000 | [diff] [blame] | 679 | /* Activity Monitor Group 1 Event Counter Registers */ |
| 680 | #define AMEVCNTR10 p15, 0, c4 |
| 681 | #define AMEVCNTR11 p15, 1, c4 |
| 682 | #define AMEVCNTR12 p15, 2, c4 |
| 683 | #define AMEVCNTR13 p15, 3, c4 |
| 684 | #define AMEVCNTR14 p15, 4, c4 |
| 685 | #define AMEVCNTR15 p15, 5, c4 |
| 686 | #define AMEVCNTR16 p15, 6, c4 |
| 687 | #define AMEVCNTR17 p15, 7, c4 |
| 688 | #define AMEVCNTR18 p15, 0, c5 |
| 689 | #define AMEVCNTR19 p15, 1, c5 |
| 690 | #define AMEVCNTR1A p15, 2, c5 |
| 691 | #define AMEVCNTR1B p15, 3, c5 |
| 692 | #define AMEVCNTR1C p15, 4, c5 |
| 693 | #define AMEVCNTR1D p15, 5, c5 |
| 694 | #define AMEVCNTR1E p15, 6, c5 |
| 695 | #define AMEVCNTR1F p15, 7, c5 |
| 696 | |
| 697 | /* Activity Monitor Group 1 Event Type Registers */ |
| 698 | #define AMEVTYPER10 p15, 0, c13, c14, 0 |
| 699 | #define AMEVTYPER11 p15, 0, c13, c14, 1 |
| 700 | #define AMEVTYPER12 p15, 0, c13, c14, 2 |
| 701 | #define AMEVTYPER13 p15, 0, c13, c14, 3 |
| 702 | #define AMEVTYPER14 p15, 0, c13, c14, 4 |
| 703 | #define AMEVTYPER15 p15, 0, c13, c14, 5 |
| 704 | #define AMEVTYPER16 p15, 0, c13, c14, 6 |
| 705 | #define AMEVTYPER17 p15, 0, c13, c14, 7 |
| 706 | #define AMEVTYPER18 p15, 0, c13, c15, 0 |
| 707 | #define AMEVTYPER19 p15, 0, c13, c15, 1 |
| 708 | #define AMEVTYPER1A p15, 0, c13, c15, 2 |
| 709 | #define AMEVTYPER1B p15, 0, c13, c15, 3 |
| 710 | #define AMEVTYPER1C p15, 0, c13, c15, 4 |
| 711 | #define AMEVTYPER1D p15, 0, c13, c15, 5 |
| 712 | #define AMEVTYPER1E p15, 0, c13, c15, 6 |
| 713 | #define AMEVTYPER1F p15, 0, c13, c15, 7 |
| 714 | |
Alexei Fedorov | 7e6306b | 2020-07-14 08:17:56 +0100 | [diff] [blame] | 715 | /* AMCFGR definitions */ |
| 716 | #define AMCFGR_NCG_SHIFT U(28) |
| 717 | #define AMCFGR_NCG_MASK U(0xf) |
| 718 | #define AMCFGR_N_SHIFT U(0) |
| 719 | #define AMCFGR_N_MASK U(0xff) |
| 720 | |
| 721 | /* AMCGCR definitions */ |
| 722 | #define AMCGCR_CG1NC_SHIFT U(8) |
| 723 | #define AMCGCR_CG1NC_MASK U(0xff) |
| 724 | |
Madhukar Pappireddy | 90d6532 | 2019-10-30 14:24:39 -0500 | [diff] [blame] | 725 | /******************************************************************************* |
| 726 | * Definitions for DynamicIQ Shared Unit registers |
| 727 | ******************************************************************************/ |
| 728 | #define CLUSTERPWRDN p15, 0, c15, c3, 6 |
| 729 | |
| 730 | /* CLUSTERPWRDN register definitions */ |
| 731 | #define DSU_CLUSTER_PWR_OFF 0 |
| 732 | #define DSU_CLUSTER_PWR_ON 1 |
| 733 | #define DSU_CLUSTER_PWR_MASK U(1) |
| 734 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 735 | #endif /* ARCH_H */ |