blob: f0ed9a6029fc2c7f9f1c1d34561dd7821706c2a5 [file] [log] [blame]
Vikram Kanigiri510d87b2016-01-29 12:32:58 +00001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arm_def.h>
32#include <assert.h>
33#include <debug.h>
34#include <platform_def.h>
35#include <tzc_dmc500.h>
36
37/*******************************************************************************
38 * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
39 * Configure both the interfaces on Region 0 with no access, Region 1 with
40 * secure access only, and the remaining DRAM regions access from the
41 * given Non-Secure masters.
42 *
43 * When booting an EL3 payload, this is simplified: we configure region 0 with
44 * secure access only and do not enable any other region.
45 ******************************************************************************/
46void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data)
47{
48 assert(plat_driver_data);
49
50 INFO("Configuring DMC-500 TZ Settings\n");
51
52 tzc_dmc500_driver_init(plat_driver_data);
53
54#ifndef EL3_PAYLOAD_BASE
55 /* Region 0 set to no access by default */
56 tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
57
58 /* Region 1 set to cover Secure part of DRAM */
59 tzc_dmc500_configure_region(1, ARM_AP_TZC_DRAM1_BASE,
60 ARM_AP_TZC_DRAM1_END,
61 TZC_REGION_S_RDWR,
62 0);
63
64 /* Region 2 set to cover Non-Secure access to 1st DRAM address range.*/
65 tzc_dmc500_configure_region(2,
66 ARM_NS_DRAM1_BASE,
67 ARM_NS_DRAM1_END,
68 TZC_REGION_S_NONE,
69 PLAT_ARM_TZC_NS_DEV_ACCESS);
70
71 /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
72 tzc_dmc500_configure_region(3,
73 ARM_DRAM2_BASE,
74 ARM_DRAM2_END,
75 TZC_REGION_S_NONE,
76 PLAT_ARM_TZC_NS_DEV_ACCESS);
77#else
78 /* Allow secure access only to DRAM for EL3 payloads */
79 tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);
80#endif
81 /*
82 * Raise an exception if a NS device tries to access secure memory
83 * TODO: Add interrupt handling support.
84 */
85 tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR);
86
87 /*
88 * Flush the configuration settings to have an affect. Validate
89 * flush by checking FILTER_EN is set on region 1 attributes
90 * register.
91 */
92 tzc_dmc500_config_complete();
93
94 /*
95 * Wait for the flush to complete.
96 * TODO: Have a timeout for this loop
97 */
98 while (tzc_dmc500_verify_complete())
99 ;
100}