Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 1 | Arm Fixed Virtual Platforms (FVP) |
| 2 | ================================= |
| 3 | |
| 4 | Fixed Virtual Platform (FVP) Support |
| 5 | ------------------------------------ |
| 6 | |
| 7 | This section lists the supported Arm |FVP| platforms. Please refer to the FVP |
| 8 | documentation for a detailed description of the model parameter options. |
| 9 | |
| 10 | The latest version of the AArch64 build of TF-A has been tested on the following |
| 11 | Arm FVPs without shifted affinities, and that do not support threaded CPU cores |
| 12 | (64-bit host machine only). |
| 13 | |
| 14 | .. note:: |
| 15 | The FVP models used are Version 11.6 Build 45, unless otherwise stated. |
| 16 | |
| 17 | - ``FVP_Base_AEMv8A-AEMv8A`` |
| 18 | - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` |
| 19 | - ``FVP_Base_RevC-2xAEMv8A`` |
| 20 | - ``FVP_Base_Cortex-A32x4`` |
| 21 | - ``FVP_Base_Cortex-A35x4`` |
| 22 | - ``FVP_Base_Cortex-A53x4`` |
| 23 | - ``FVP_Base_Cortex-A55x4+Cortex-A75x4`` |
| 24 | - ``FVP_Base_Cortex-A55x4`` |
| 25 | - ``FVP_Base_Cortex-A57x1-A53x1`` |
| 26 | - ``FVP_Base_Cortex-A57x2-A53x4`` |
| 27 | - ``FVP_Base_Cortex-A57x4-A53x4`` |
| 28 | - ``FVP_Base_Cortex-A57x4`` |
| 29 | - ``FVP_Base_Cortex-A72x4-A53x4`` |
| 30 | - ``FVP_Base_Cortex-A72x4`` |
| 31 | - ``FVP_Base_Cortex-A73x4-A53x4`` |
| 32 | - ``FVP_Base_Cortex-A73x4`` |
| 33 | - ``FVP_Base_Cortex-A75x4`` |
| 34 | - ``FVP_Base_Cortex-A76x4`` |
| 35 | - ``FVP_Base_Cortex-A76AEx4`` |
| 36 | - ``FVP_Base_Cortex-A76AEx8`` |
| 37 | - ``FVP_Base_Cortex-A77x4`` (Version 11.7 build 36) |
| 38 | - ``FVP_Base_Neoverse-N1x4`` |
| 39 | - ``FVP_Base_Zeusx4`` |
| 40 | - ``FVP_CSS_SGI-575`` (Version 11.3 build 42) |
| 41 | - ``FVP_CSS_SGM-775`` (Version 11.3 build 42) |
| 42 | - ``FVP_RD_E1Edge`` (Version 11.3 build 42) |
| 43 | - ``FVP_RD_N1Edge`` |
| 44 | - ``Foundation_Platform`` |
| 45 | |
| 46 | The latest version of the AArch32 build of TF-A has been tested on the |
| 47 | following Arm FVPs without shifted affinities, and that do not support threaded |
| 48 | CPU cores (64-bit host machine only). |
| 49 | |
| 50 | - ``FVP_Base_AEMv8A-AEMv8A`` |
| 51 | - ``FVP_Base_Cortex-A32x4`` |
| 52 | |
| 53 | .. note:: |
| 54 | The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which |
| 55 | is not compatible with legacy GIC configurations. Therefore this FVP does not |
| 56 | support these legacy GIC configurations. |
| 57 | |
| 58 | The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm |
| 59 | FVP website`_. The Cortex-A models listed above are also available to download |
| 60 | from `Arm's website`_. |
| 61 | |
| 62 | .. note:: |
| 63 | The build numbers quoted above are those reported by launching the FVP |
| 64 | with the ``--version`` parameter. |
| 65 | |
| 66 | .. note:: |
| 67 | Linaro provides a ramdisk image in prebuilt FVP configurations and full |
| 68 | file systems that can be downloaded separately. To run an FVP with a virtio |
| 69 | file system image an additional FVP configuration option |
| 70 | ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be |
| 71 | used. |
| 72 | |
| 73 | .. note:: |
| 74 | The software will not work on Version 1.0 of the Foundation FVP. |
| 75 | The commands below would report an ``unhandled argument`` error in this case. |
| 76 | |
| 77 | .. note:: |
| 78 | FVPs can be launched with ``--cadi-server`` option such that a |
| 79 | CADI-compliant debugger (for example, Arm DS-5) can connect to and control |
| 80 | its execution. |
| 81 | |
| 82 | .. warning:: |
| 83 | Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202 |
| 84 | the internal synchronisation timings changed compared to older versions of |
| 85 | the models. The models can be launched with ``-Q 100`` option if they are |
| 86 | required to match the run time characteristics of the older versions. |
| 87 | |
| 88 | All the above platforms have been tested with `Linaro Release 19.06`_. |
| 89 | |
| 90 | .. _build_options_arm_fvp_platform: |
| 91 | |
| 92 | Arm FVP Platform Specific Build Options |
| 93 | --------------------------------------- |
| 94 | |
| 95 | - ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to |
| 96 | build the topology tree within TF-A. By default TF-A is configured for dual |
| 97 | cluster topology and this option can be used to override the default value. |
| 98 | |
| 99 | - ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The |
| 100 | default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as |
| 101 | explained in the options below: |
| 102 | |
| 103 | - ``FVP_CCI`` : The CCI driver is selected. This is the default |
| 104 | if 0 < ``FVP_CLUSTER_COUNT`` <= 2. |
| 105 | - ``FVP_CCN`` : The CCN driver is selected. This is the default |
| 106 | if ``FVP_CLUSTER_COUNT`` > 2. |
| 107 | |
| 108 | - ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in |
| 109 | a single cluster. This option defaults to 4. |
| 110 | |
| 111 | - ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU |
| 112 | in the system. This option defaults to 1. Note that the build option |
| 113 | ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms. |
| 114 | |
| 115 | - ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options: |
| 116 | |
| 117 | - ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected |
| 118 | - ``FVP_GICV2`` : The GICv2 only driver is selected |
| 119 | - ``FVP_GICV3`` : The GICv3 only driver is selected (default option) |
| 120 | |
| 121 | - ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer |
| 122 | for functions that wait for an arbitrary time length (udelay and mdelay). |
| 123 | The default value is 0. |
| 124 | |
| 125 | - ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled |
| 126 | to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for |
| 127 | details on HW_CONFIG. By default, this is initialized to a sensible DTS |
| 128 | file in ``fdts/`` folder depending on other build options. But some cases, |
| 129 | like shifted affinity format for MPIDR, cannot be detected at build time |
| 130 | and this option is needed to specify the appropriate DTS file. |
| 131 | |
| 132 | - ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in |
| 133 | FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is |
| 134 | similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the |
| 135 | HW_CONFIG blob instead of the DTS file. This option is useful to override |
| 136 | the default HW_CONFIG selected by the build system. |
| 137 | |
| 138 | Booting Firmware Update images |
| 139 | ------------------------------ |
| 140 | |
| 141 | When Firmware Update (FWU) is enabled there are at least 2 new images |
| 142 | that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the |
| 143 | FWU FIP. |
| 144 | |
| 145 | The additional fip images must be loaded with: |
| 146 | |
| 147 | :: |
| 148 | |
| 149 | --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address] |
| 150 | --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address] |
| 151 | |
| 152 | The address ns_bl1u_base_address is the value of NS_BL1U_BASE. |
| 153 | In the same way, the address ns_bl2u_base_address is the value of |
| 154 | NS_BL2U_BASE. |
| 155 | |
| 156 | Booting an EL3 payload |
| 157 | ---------------------- |
| 158 | |
| 159 | The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for |
| 160 | the secondary CPUs holding pen to work properly. Unfortunately, its reset value |
| 161 | is undefined on the FVP platform and the FVP platform code doesn't clear it. |
| 162 | Therefore, one must modify the way the model is normally invoked in order to |
| 163 | clear the mailbox at start-up. |
| 164 | |
| 165 | One way to do that is to create an 8-byte file containing all zero bytes using |
| 166 | the following command: |
| 167 | |
| 168 | .. code:: shell |
| 169 | |
| 170 | dd if=/dev/zero of=mailbox.dat bs=1 count=8 |
| 171 | |
| 172 | and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``) |
| 173 | using the following model parameters: |
| 174 | |
| 175 | :: |
| 176 | |
| 177 | --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] |
| 178 | --data=mailbox.dat@0x04000000 [Foundation FVP] |
| 179 | |
| 180 | To provide the model with the EL3 payload image, the following methods may be |
| 181 | used: |
| 182 | |
| 183 | #. If the EL3 payload is able to execute in place, it may be programmed into |
| 184 | flash memory. On Base Cortex and AEM FVPs, the following model parameter |
| 185 | loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already |
| 186 | used for the FIP): |
| 187 | |
| 188 | :: |
| 189 | |
| 190 | -C bp.flashloader1.fname="<path-to>/<el3-payload>" |
| 191 | |
| 192 | On Foundation FVP, there is no flash loader component and the EL3 payload |
| 193 | may be programmed anywhere in flash using method 3 below. |
| 194 | |
| 195 | #. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5 |
| 196 | command may be used to load the EL3 payload ELF image over JTAG: |
| 197 | |
| 198 | :: |
| 199 | |
| 200 | load <path-to>/el3-payload.elf |
| 201 | |
| 202 | #. The EL3 payload may be pre-loaded in volatile memory using the following |
| 203 | model parameters: |
| 204 | |
| 205 | :: |
| 206 | |
| 207 | --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs] |
| 208 | --data="<path-to>/<el3-payload>"@address [Foundation FVP] |
| 209 | |
| 210 | The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address |
| 211 | used when building TF-A. |
| 212 | |
| 213 | Booting a preloaded kernel image (Base FVP) |
| 214 | ------------------------------------------- |
| 215 | |
| 216 | The following example uses a simplified boot flow by directly jumping from the |
| 217 | TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be |
| 218 | useful if both the kernel and the device tree blob (DTB) are already present in |
| 219 | memory (like in FVP). |
| 220 | |
| 221 | For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at |
| 222 | address ``0x82000000``, the firmware can be built like this: |
| 223 | |
| 224 | .. code:: shell |
| 225 | |
Mark Dykes | ef3a456 | 2020-01-08 20:37:18 +0000 | [diff] [blame^] | 226 | CROSS_COMPILE=aarch64-linux-gnu- \ |
Paul Beesley | d2fcc4e | 2019-05-29 13:59:40 +0100 | [diff] [blame] | 227 | make PLAT=fvp DEBUG=1 \ |
| 228 | RESET_TO_BL31=1 \ |
| 229 | ARM_LINUX_KERNEL_AS_BL33=1 \ |
| 230 | PRELOADED_BL33_BASE=0x80080000 \ |
| 231 | ARM_PRELOADED_DTB_BASE=0x82000000 \ |
| 232 | all fip |
| 233 | |
| 234 | Now, it is needed to modify the DTB so that the kernel knows the address of the |
| 235 | ramdisk. The following script generates a patched DTB from the provided one, |
| 236 | assuming that the ramdisk is loaded at address ``0x84000000``. Note that this |
| 237 | script assumes that the user is using a ramdisk image prepared for U-Boot, like |
| 238 | the ones provided by Linaro. If using a ramdisk without this header,the ``0x40`` |
| 239 | offset in ``INITRD_START`` has to be removed. |
| 240 | |
| 241 | .. code:: bash |
| 242 | |
| 243 | #!/bin/bash |
| 244 | |
| 245 | # Path to the input DTB |
| 246 | KERNEL_DTB=<path-to>/<fdt> |
| 247 | # Path to the output DTB |
| 248 | PATCHED_KERNEL_DTB=<path-to>/<patched-fdt> |
| 249 | # Base address of the ramdisk |
| 250 | INITRD_BASE=0x84000000 |
| 251 | # Path to the ramdisk |
| 252 | INITRD=<path-to>/<ramdisk.img> |
| 253 | |
| 254 | # Skip uboot header (64 bytes) |
| 255 | INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) ) |
| 256 | INITRD_SIZE=$(stat -Lc %s ${INITRD}) |
| 257 | INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) ) |
| 258 | |
| 259 | CHOSEN_NODE=$(echo \ |
| 260 | "/ { \ |
| 261 | chosen { \ |
| 262 | linux,initrd-start = <${INITRD_START}>; \ |
| 263 | linux,initrd-end = <${INITRD_END}>; \ |
| 264 | }; \ |
| 265 | };") |
| 266 | |
| 267 | echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \ |
| 268 | dtc -O dtb -o ${PATCHED_KERNEL_DTB} - |
| 269 | |
| 270 | And the FVP binary can be run with the following command: |
| 271 | |
| 272 | .. code:: shell |
| 273 | |
| 274 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 275 | -C pctl.startup=0.0.0.0 \ |
| 276 | -C bp.secure_memory=1 \ |
| 277 | -C cluster0.NUM_CORES=4 \ |
| 278 | -C cluster1.NUM_CORES=4 \ |
| 279 | -C cache_state_modelled=1 \ |
| 280 | -C cluster0.cpu0.RVBAR=0x04020000 \ |
| 281 | -C cluster0.cpu1.RVBAR=0x04020000 \ |
| 282 | -C cluster0.cpu2.RVBAR=0x04020000 \ |
| 283 | -C cluster0.cpu3.RVBAR=0x04020000 \ |
| 284 | -C cluster1.cpu0.RVBAR=0x04020000 \ |
| 285 | -C cluster1.cpu1.RVBAR=0x04020000 \ |
| 286 | -C cluster1.cpu2.RVBAR=0x04020000 \ |
| 287 | -C cluster1.cpu3.RVBAR=0x04020000 \ |
| 288 | --data cluster0.cpu0="<path-to>/bl31.bin"@0x04020000 \ |
| 289 | --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \ |
| 290 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 291 | --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000 |
| 292 | |
| 293 | Obtaining the Flattened Device Trees |
| 294 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 295 | |
| 296 | Depending on the FVP configuration and Linux configuration used, different |
| 297 | FDT files are required. FDT source files for the Foundation and Base FVPs can |
| 298 | be found in the TF-A source directory under ``fdts/``. The Foundation FVP has |
| 299 | a subset of the Base FVP components. For example, the Foundation FVP lacks |
| 300 | CLCD and MMC support, and has only one CPU cluster. |
| 301 | |
| 302 | .. note:: |
| 303 | It is not recommended to use the FDTs built along the kernel because not |
| 304 | all FDTs are available from there. |
| 305 | |
| 306 | The dynamic configuration capability is enabled in the firmware for FVPs. |
| 307 | This means that the firmware can authenticate and load the FDT if present in |
| 308 | FIP. A default FDT is packaged into FIP during the build based on |
| 309 | the build configuration. This can be overridden by using the ``FVP_HW_CONFIG`` |
| 310 | or ``FVP_HW_CONFIG_DTS`` build options (refer to |
| 311 | :ref:`build_options_arm_fvp_platform` for details on the options). |
| 312 | |
| 313 | - ``fvp-base-gicv2-psci.dts`` |
| 314 | |
| 315 | For use with models such as the Cortex-A57-A53 Base FVPs without shifted |
| 316 | affinities and with Base memory map configuration. |
| 317 | |
| 318 | - ``fvp-base-gicv2-psci-aarch32.dts`` |
| 319 | |
| 320 | For use with models such as the Cortex-A32 Base FVPs without shifted |
| 321 | affinities and running Linux in AArch32 state with Base memory map |
| 322 | configuration. |
| 323 | |
| 324 | - ``fvp-base-gicv3-psci.dts`` |
| 325 | |
| 326 | For use with models such as the Cortex-A57-A53 Base FVPs without shifted |
| 327 | affinities and with Base memory map configuration and Linux GICv3 support. |
| 328 | |
| 329 | - ``fvp-base-gicv3-psci-1t.dts`` |
| 330 | |
| 331 | For use with models such as the AEMv8-RevC Base FVP with shifted affinities, |
| 332 | single threaded CPUs, Base memory map configuration and Linux GICv3 support. |
| 333 | |
| 334 | - ``fvp-base-gicv3-psci-dynamiq.dts`` |
| 335 | |
| 336 | For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities, |
| 337 | single cluster, single threaded CPUs, Base memory map configuration and Linux |
| 338 | GICv3 support. |
| 339 | |
| 340 | - ``fvp-base-gicv3-psci-aarch32.dts`` |
| 341 | |
| 342 | For use with models such as the Cortex-A32 Base FVPs without shifted |
| 343 | affinities and running Linux in AArch32 state with Base memory map |
| 344 | configuration and Linux GICv3 support. |
| 345 | |
| 346 | - ``fvp-foundation-gicv2-psci.dts`` |
| 347 | |
| 348 | For use with Foundation FVP with Base memory map configuration. |
| 349 | |
| 350 | - ``fvp-foundation-gicv3-psci.dts`` |
| 351 | |
| 352 | (Default) For use with Foundation FVP with Base memory map configuration |
| 353 | and Linux GICv3 support. |
| 354 | |
| 355 | |
| 356 | Running on the Foundation FVP with reset to BL1 entrypoint |
| 357 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 358 | |
| 359 | The following ``Foundation_Platform`` parameters should be used to boot Linux with |
| 360 | 4 CPUs using the AArch64 build of TF-A. |
| 361 | |
| 362 | .. code:: shell |
| 363 | |
| 364 | <path-to>/Foundation_Platform \ |
| 365 | --cores=4 \ |
| 366 | --arm-v8.0 \ |
| 367 | --secure-memory \ |
| 368 | --visualization \ |
| 369 | --gicv3 \ |
| 370 | --data="<path-to>/<bl1-binary>"@0x0 \ |
| 371 | --data="<path-to>/<FIP-binary>"@0x08000000 \ |
| 372 | --data="<path-to>/<kernel-binary>"@0x80080000 \ |
| 373 | --data="<path-to>/<ramdisk-binary>"@0x84000000 |
| 374 | |
| 375 | Notes: |
| 376 | |
| 377 | - BL1 is loaded at the start of the Trusted ROM. |
| 378 | - The Firmware Image Package is loaded at the start of NOR FLASH0. |
| 379 | - The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address |
| 380 | is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_. |
| 381 | - The default use-case for the Foundation FVP is to use the ``--gicv3`` option |
| 382 | and enable the GICv3 device in the model. Note that without this option, |
| 383 | the Foundation FVP defaults to legacy (Versatile Express) memory map which |
| 384 | is not supported by TF-A. |
| 385 | - In order for TF-A to run correctly on the Foundation FVP, the architecture |
| 386 | versions must match. The Foundation FVP defaults to the highest v8.x |
| 387 | version it supports but the default build for TF-A is for v8.0. To avoid |
| 388 | issues either start the Foundation FVP to use v8.0 architecture using the |
| 389 | ``--arm-v8.0`` option, or build TF-A with an appropriate value for |
| 390 | ``ARM_ARCH_MINOR``. |
| 391 | |
| 392 | Running on the AEMv8 Base FVP with reset to BL1 entrypoint |
| 393 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 394 | |
| 395 | The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux |
| 396 | with 8 CPUs using the AArch64 build of TF-A. |
| 397 | |
| 398 | .. code:: shell |
| 399 | |
| 400 | <path-to>/FVP_Base_RevC-2xAEMv8A \ |
| 401 | -C pctl.startup=0.0.0.0 \ |
| 402 | -C bp.secure_memory=1 \ |
| 403 | -C bp.tzc_400.diagnostics=1 \ |
| 404 | -C cluster0.NUM_CORES=4 \ |
| 405 | -C cluster1.NUM_CORES=4 \ |
| 406 | -C cache_state_modelled=1 \ |
| 407 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 408 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
| 409 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 410 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 411 | |
| 412 | .. note:: |
| 413 | The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires |
| 414 | a specific DTS for all the CPUs to be loaded. |
| 415 | |
| 416 | Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint |
| 417 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 418 | |
| 419 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
| 420 | with 8 CPUs using the AArch32 build of TF-A. |
| 421 | |
| 422 | .. code:: shell |
| 423 | |
| 424 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 425 | -C pctl.startup=0.0.0.0 \ |
| 426 | -C bp.secure_memory=1 \ |
| 427 | -C bp.tzc_400.diagnostics=1 \ |
| 428 | -C cluster0.NUM_CORES=4 \ |
| 429 | -C cluster1.NUM_CORES=4 \ |
| 430 | -C cache_state_modelled=1 \ |
| 431 | -C cluster0.cpu0.CONFIG64=0 \ |
| 432 | -C cluster0.cpu1.CONFIG64=0 \ |
| 433 | -C cluster0.cpu2.CONFIG64=0 \ |
| 434 | -C cluster0.cpu3.CONFIG64=0 \ |
| 435 | -C cluster1.cpu0.CONFIG64=0 \ |
| 436 | -C cluster1.cpu1.CONFIG64=0 \ |
| 437 | -C cluster1.cpu2.CONFIG64=0 \ |
| 438 | -C cluster1.cpu3.CONFIG64=0 \ |
| 439 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 440 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
| 441 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 442 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 443 | |
| 444 | Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint |
| 445 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 446 | |
| 447 | The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to |
| 448 | boot Linux with 8 CPUs using the AArch64 build of TF-A. |
| 449 | |
| 450 | .. code:: shell |
| 451 | |
| 452 | <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ |
| 453 | -C pctl.startup=0.0.0.0 \ |
| 454 | -C bp.secure_memory=1 \ |
| 455 | -C bp.tzc_400.diagnostics=1 \ |
| 456 | -C cache_state_modelled=1 \ |
| 457 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 458 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
| 459 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 460 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 461 | |
| 462 | Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint |
| 463 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 464 | |
| 465 | The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to |
| 466 | boot Linux with 4 CPUs using the AArch32 build of TF-A. |
| 467 | |
| 468 | .. code:: shell |
| 469 | |
| 470 | <path-to>/FVP_Base_Cortex-A32x4 \ |
| 471 | -C pctl.startup=0.0.0.0 \ |
| 472 | -C bp.secure_memory=1 \ |
| 473 | -C bp.tzc_400.diagnostics=1 \ |
| 474 | -C cache_state_modelled=1 \ |
| 475 | -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ |
| 476 | -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ |
| 477 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 478 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 479 | |
| 480 | |
| 481 | Running on the AEMv8 Base FVP with reset to BL31 entrypoint |
| 482 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 483 | |
| 484 | The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux |
| 485 | with 8 CPUs using the AArch64 build of TF-A. |
| 486 | |
| 487 | .. code:: shell |
| 488 | |
| 489 | <path-to>/FVP_Base_RevC-2xAEMv8A \ |
| 490 | -C pctl.startup=0.0.0.0 \ |
| 491 | -C bp.secure_memory=1 \ |
| 492 | -C bp.tzc_400.diagnostics=1 \ |
| 493 | -C cluster0.NUM_CORES=4 \ |
| 494 | -C cluster1.NUM_CORES=4 \ |
| 495 | -C cache_state_modelled=1 \ |
| 496 | -C cluster0.cpu0.RVBAR=0x04010000 \ |
| 497 | -C cluster0.cpu1.RVBAR=0x04010000 \ |
| 498 | -C cluster0.cpu2.RVBAR=0x04010000 \ |
| 499 | -C cluster0.cpu3.RVBAR=0x04010000 \ |
| 500 | -C cluster1.cpu0.RVBAR=0x04010000 \ |
| 501 | -C cluster1.cpu1.RVBAR=0x04010000 \ |
| 502 | -C cluster1.cpu2.RVBAR=0x04010000 \ |
| 503 | -C cluster1.cpu3.RVBAR=0x04010000 \ |
| 504 | --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ |
| 505 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ |
| 506 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
| 507 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
| 508 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 509 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 510 | |
| 511 | Notes: |
| 512 | |
| 513 | - If Position Independent Executable (PIE) support is enabled for BL31 |
| 514 | in this config, it can be loaded at any valid address for execution. |
| 515 | |
| 516 | - Since a FIP is not loaded when using BL31 as reset entrypoint, the |
| 517 | ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>`` |
| 518 | parameter is needed to load the individual bootloader images in memory. |
| 519 | BL32 image is only needed if BL31 has been built to expect a Secure-EL1 |
| 520 | Payload. For the same reason, the FDT needs to be compiled from the DT source |
| 521 | and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000`` |
| 522 | parameter. |
| 523 | |
| 524 | - The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a |
| 525 | specific DTS for all the CPUs to be loaded. |
| 526 | |
| 527 | - The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where |
| 528 | X and Y are the cluster and CPU numbers respectively, is used to set the |
| 529 | reset vector for each core. |
| 530 | |
| 531 | - Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require |
| 532 | changing the value of |
| 533 | ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of |
| 534 | ``BL32_BASE``. |
| 535 | |
| 536 | |
| 537 | Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint |
| 538 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 539 | |
| 540 | The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux |
| 541 | with 8 CPUs using the AArch32 build of TF-A. |
| 542 | |
| 543 | .. code:: shell |
| 544 | |
| 545 | <path-to>/FVP_Base_AEMv8A-AEMv8A \ |
| 546 | -C pctl.startup=0.0.0.0 \ |
| 547 | -C bp.secure_memory=1 \ |
| 548 | -C bp.tzc_400.diagnostics=1 \ |
| 549 | -C cluster0.NUM_CORES=4 \ |
| 550 | -C cluster1.NUM_CORES=4 \ |
| 551 | -C cache_state_modelled=1 \ |
| 552 | -C cluster0.cpu0.CONFIG64=0 \ |
| 553 | -C cluster0.cpu1.CONFIG64=0 \ |
| 554 | -C cluster0.cpu2.CONFIG64=0 \ |
| 555 | -C cluster0.cpu3.CONFIG64=0 \ |
| 556 | -C cluster1.cpu0.CONFIG64=0 \ |
| 557 | -C cluster1.cpu1.CONFIG64=0 \ |
| 558 | -C cluster1.cpu2.CONFIG64=0 \ |
| 559 | -C cluster1.cpu3.CONFIG64=0 \ |
| 560 | -C cluster0.cpu0.RVBAR=0x04002000 \ |
| 561 | -C cluster0.cpu1.RVBAR=0x04002000 \ |
| 562 | -C cluster0.cpu2.RVBAR=0x04002000 \ |
| 563 | -C cluster0.cpu3.RVBAR=0x04002000 \ |
| 564 | -C cluster1.cpu0.RVBAR=0x04002000 \ |
| 565 | -C cluster1.cpu1.RVBAR=0x04002000 \ |
| 566 | -C cluster1.cpu2.RVBAR=0x04002000 \ |
| 567 | -C cluster1.cpu3.RVBAR=0x04002000 \ |
| 568 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ |
| 569 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
| 570 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
| 571 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 572 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 573 | |
| 574 | .. note:: |
| 575 | The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``. |
| 576 | It should match the address programmed into the RVBAR register as well. |
| 577 | |
| 578 | Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint |
| 579 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 580 | |
| 581 | The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to |
| 582 | boot Linux with 8 CPUs using the AArch64 build of TF-A. |
| 583 | |
| 584 | .. code:: shell |
| 585 | |
| 586 | <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ |
| 587 | -C pctl.startup=0.0.0.0 \ |
| 588 | -C bp.secure_memory=1 \ |
| 589 | -C bp.tzc_400.diagnostics=1 \ |
| 590 | -C cache_state_modelled=1 \ |
| 591 | -C cluster0.cpu0.RVBARADDR=0x04010000 \ |
| 592 | -C cluster0.cpu1.RVBARADDR=0x04010000 \ |
| 593 | -C cluster0.cpu2.RVBARADDR=0x04010000 \ |
| 594 | -C cluster0.cpu3.RVBARADDR=0x04010000 \ |
| 595 | -C cluster1.cpu0.RVBARADDR=0x04010000 \ |
| 596 | -C cluster1.cpu1.RVBARADDR=0x04010000 \ |
| 597 | -C cluster1.cpu2.RVBARADDR=0x04010000 \ |
| 598 | -C cluster1.cpu3.RVBARADDR=0x04010000 \ |
| 599 | --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ |
| 600 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ |
| 601 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
| 602 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
| 603 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 604 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 605 | |
| 606 | Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint |
| 607 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 608 | |
| 609 | The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to |
| 610 | boot Linux with 4 CPUs using the AArch32 build of TF-A. |
| 611 | |
| 612 | .. code:: shell |
| 613 | |
| 614 | <path-to>/FVP_Base_Cortex-A32x4 \ |
| 615 | -C pctl.startup=0.0.0.0 \ |
| 616 | -C bp.secure_memory=1 \ |
| 617 | -C bp.tzc_400.diagnostics=1 \ |
| 618 | -C cache_state_modelled=1 \ |
| 619 | -C cluster0.cpu0.RVBARADDR=0x04002000 \ |
| 620 | -C cluster0.cpu1.RVBARADDR=0x04002000 \ |
| 621 | -C cluster0.cpu2.RVBARADDR=0x04002000 \ |
| 622 | -C cluster0.cpu3.RVBARADDR=0x04002000 \ |
| 623 | --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \ |
| 624 | --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ |
| 625 | --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ |
| 626 | --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ |
| 627 | --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 |
| 628 | |
| 629 | -------------- |
| 630 | |
| 631 | *Copyright (c) 2019, Arm Limited. All rights reserved.* |
| 632 | |
| 633 | .. _TB_FW_CONFIG for FVP: ../plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts |
| 634 | .. _Arm's website: `FVP models`_ |
| 635 | .. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms |
| 636 | .. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06 |
| 637 | .. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms |