| Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2021 NXP |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef SOC_DEFAULT_HELPER_MACROS_H |
| 9 | #define SOC_DEFAULT_HELPER_MACROS_H |
| 10 | |
| 11 | #ifdef NXP_OCRAM_TZPC_ADDR |
| 12 | |
| 13 | /* 0x1: means 4 KB |
| 14 | * 0x2: means 8 KB |
| 15 | */ |
| 16 | #define TZPC_BLOCK_SIZE 0x1000 |
| 17 | #endif |
| 18 | |
| 19 | /* DDR controller offsets and defines */ |
| 20 | #ifdef NXP_DDR_ADDR |
| 21 | |
| 22 | #define DDR_CFG_2_OFFSET 0x114 |
| 23 | #define CFG_2_FORCE_REFRESH 0x80000000 |
| 24 | |
| 25 | #endif /* NXP_DDR_ADDR */ |
| 26 | |
| 27 | /* Reset block register offsets */ |
| 28 | #ifdef NXP_RESET_ADDR |
| 29 | |
| 30 | /* Register Offset */ |
| 31 | #define RST_RSTCR_OFFSET 0x0 |
| 32 | #define RST_RSTRQMR1_OFFSET 0x10 |
| 33 | #define RST_RSTRQSR1_OFFSET 0x18 |
| 34 | #define BRR_OFFSET 0x60 |
| 35 | |
| 36 | /* helper macros */ |
| 37 | #define RSTRQSR1_SWRR 0x800 |
| 38 | #define RSTRQMR_RPTOE_MASK (1 << 19) |
| 39 | |
| 40 | #endif /* NXP_RESET_ADDR */ |
| 41 | |
| Jiafei Pan | 40b6d86 | 2021-09-10 19:13:27 +0800 | [diff] [blame] | 42 | /* secmon register offsets and bitfields */ |
| 43 | #define SECMON_HPCOMR_OFFSET 0x4 |
| 44 | #define SECMON_HPCOMR_NPSWAEN 0x80000000 |
| 45 | |
| Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 46 | /* Secure-Register-File register offsets and bit masks */ |
| 47 | #ifdef NXP_RST_ADDR |
| 48 | /* Register Offset */ |
| 49 | #define CORE_HOLD_OFFSET 0x140 |
| 50 | #define RSTCNTL_OFFSET 0x180 |
| 51 | |
| 52 | /* Helper macros */ |
| 53 | #define SW_RST_REQ_INIT 0x1 |
| 54 | #endif |
| 55 | |
| 56 | #ifdef NXP_CCN_ADDR |
| 57 | #define NXP_CCN_HN_F_1_ADDR 0x04210000 |
| 58 | |
| 59 | #define CCN_HN_F_SAM_NODEID_MASK 0x7f |
| 60 | #define CCN_HN_F_SNP_DMN_CTL_OFFSET 0x200 |
| 61 | #define CCN_HN_F_SNP_DMN_CTL_SET_OFFSET 0x210 |
| 62 | #define CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET 0x220 |
| 63 | #define CCN_HN_F_SNP_DMN_CTL_MASK 0x80a00 |
| 64 | #define CCN_HNF_NODE_COUNT 8 |
| 65 | #define CCN_HNF_OFFSET 0x10000 |
| 66 | |
| 67 | #define SA_AUX_CTRL_REG_OFFSET 0x500 |
| 68 | #define NUM_HNI_NODE 2 |
| 69 | #define CCN_HNI_MEMORY_MAP_SIZE 0x10000 |
| 70 | |
| 71 | #define PCIeRC_RN_I_NODE_ID_OFFSET 0x8 |
| 72 | #define PoS_CONTROL_REG_OFFSET 0x0 |
| 73 | #define POS_EARLY_WR_COMP_EN 0x20 |
| 74 | #define HNI_POS_EN 0x01 |
| 75 | #define POS_TERMINATE_BARRIERS 0x10 |
| 76 | #define SERIALIZE_DEV_nGnRnE_WRITES 0x200 |
| 77 | #define ENABLE_ERR_SIGNAL_TO_MN 0x4 |
| 78 | #define ENABLE_RESERVE_BIT53 0x400 |
| 79 | #define ENABLE_WUO 0x10 |
| 80 | #endif /* NXP_CCN_ADDR */ |
| 81 | |
| Jiafei Pan | 64e2ba7 | 2021-09-27 12:18:41 +0800 | [diff] [blame] | 82 | #define DCFG_SBEESR2_ADDR 0x00100534 |
| 83 | #define DCFG_MBEESR2_ADDR 0x00100544 |
| 84 | /* SBEESR and MBEESR bit mask */ |
| 85 | #define OCRAM_EESR_MASK 0x00000008 |
| 86 | |
| Pankaj Gupta | 82bd843 | 2020-12-09 14:02:41 +0530 | [diff] [blame] | 87 | #endif /* SOC_DEFAULT_HELPER_MACROS_H */ |