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Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00005 */
6
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +01007#ifndef XLAT_MMU_HELPERS_H
8#define XLAT_MMU_HELPERS_H
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +00009
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000010/*
11 * The following flags are passed to enable_mmu_xxx() to override the default
12 * values used to program system registers while enabling the MMU.
13 */
14
15/*
16 * When this flag is used, all data access to Normal memory from this EL and all
17 * Normal memory accesses to the translation tables of this EL are non-cacheable
18 * for all levels of data and unified cache until the caches are enabled by
19 * setting the bit SCTLR_ELx.C.
20 */
21#define DISABLE_DCACHE (U(1) << 0)
22
23/*
24 * Mark the translation tables as non-cacheable for the MMU table walker, which
25 * is a different observer from the PE/CPU. If the flag is not specified, the
26 * tables are cacheable for the MMU table walker.
27 *
28 * Note that, as far as the PE/CPU observer is concerned, the attributes used
29 * are the ones specified in the translation tables themselves. The MAIR
30 * register specifies the cacheability through the field AttrIndx of the lower
31 * attributes of the translation tables. The shareability is specified in the SH
32 * field of the lower attributes.
33 *
34 * The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn
35 * and SHn of the TCR register to access the translation tables.
36 *
37 * The attributes specified in the TCR register and the tables can be different
38 * as there are no checks to prevent that. Special care must be taken to ensure
39 * that there aren't mismatches. The behaviour in that case is described in the
40 * sections 'Mismatched memory attributes' in the ARMv8 ARM.
41 */
42#define XLAT_TABLE_NC (U(1) << 1)
43
Antonio Nino Diaz67f799e2018-07-15 16:42:01 +010044/*
45 * Offsets into a mmu_cfg_params array generated by setup_mmu_cfg(). All
46 * parameters are 64 bits wide.
47 */
48#define MMU_CFG_MAIR 0
49#define MMU_CFG_TCR 1
50#define MMU_CFG_TTBR0 2
51#define MMU_CFG_PARAM_MAX 3
52
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000053#ifndef __ASSEMBLY__
54
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +010055#include <stdbool.h>
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010056#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010057#include <string.h>
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010058
Antonio Nino Diaz67f799e2018-07-15 16:42:01 +010059/*
60 * Return the values that the MMU configuration registers must contain for the
61 * specified translation context. `params` must be a pointer to array of size
62 * MMU_CFG_PARAM_MAX.
63 */
64void setup_mmu_cfg(uint64_t *params, unsigned int flags,
65 const uint64_t *base_table, unsigned long long max_pa,
66 uintptr_t max_va, int xlat_regime);
67
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000068#ifdef AARCH32
69/* AArch32 specific translation table API */
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010070#if !ERROR_DEPRECATED
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000071void enable_mmu_secure(unsigned int flags);
Jeenu Viswambharan58e81482018-04-27 15:06:57 +010072void enable_mmu_direct(unsigned int flags);
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010073#endif
74
75void enable_mmu_svc_mon(unsigned int flags);
76void enable_mmu_hyp(unsigned int flags);
77
78void enable_mmu_direct_svc_mon(unsigned int flags);
79void enable_mmu_direct_hyp(unsigned int flags);
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000080#else
81/* AArch64 specific translation table APIs */
82void enable_mmu_el1(unsigned int flags);
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010083void enable_mmu_el2(unsigned int flags);
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000084void enable_mmu_el3(unsigned int flags);
Jeenu Viswambharan58e81482018-04-27 15:06:57 +010085
86void enable_mmu_direct_el1(unsigned int flags);
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +010087void enable_mmu_direct_el2(unsigned int flags);
Jeenu Viswambharan58e81482018-04-27 15:06:57 +010088void enable_mmu_direct_el3(unsigned int flags);
Antonio Nino Diaz233c7c12017-03-08 14:40:23 +000089#endif /* AARCH32 */
90
Antonio Nino Diaz5c97bd12018-08-02 09:57:29 +010091bool xlat_arch_is_granule_size_supported(size_t size);
Antonio Nino Diaz4413ad52018-06-11 13:40:32 +010092size_t xlat_arch_get_max_supported_granule_size(void);
93
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +000094#endif /* __ASSEMBLY__ */
95
Antonio Nino Diaz50eb3742018-07-24 10:20:53 +010096#endif /* XLAT_MMU_HELPERS_H */