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Varun Wadekarb316e242015-05-19 16:48:04 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <debug.h>
34#include <mmio.h>
35#include <pmc.h>
36#include <tegra_def.h>
37
38/* Module IDs used during power ungate procedure */
39static const int pmc_cpu_powergate_id[4] = {
40 0, /* CPU 0 */
41 9, /* CPU 1 */
42 10, /* CPU 2 */
43 11 /* CPU 3 */
44};
45
46/*******************************************************************************
47 * Power ungate CPU to start the boot process. CPU reset vectors must be
48 * populated before calling this function.
49 ******************************************************************************/
50void tegra_pmc_cpu_on(int cpu)
51{
52 uint32_t val;
53
54 /*
Varun Wadekarfccf8e02015-07-16 10:35:12 +053055 * Check if CPU is already power ungated
56 */
57 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
58 if (val & (1 << pmc_cpu_powergate_id[cpu]))
59 return;
60
61 /*
Varun Wadekarb316e242015-05-19 16:48:04 +053062 * The PMC deasserts the START bit when it starts the power
63 * ungate process. Loop till no power toggle is in progress.
64 */
65 do {
66 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
67 } while (val & PMC_TOGGLE_START);
68
69 /*
70 * Start the power ungate procedure
71 */
72 val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START;
73 tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val);
74
75 /*
76 * The PMC deasserts the START bit when it starts the power
77 * ungate process. Loop till powergate START bit is asserted.
78 */
79 do {
80 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE);
81 } while (val & (1 << 8));
82
83 /* loop till the CPU is power ungated */
84 do {
85 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS);
86 } while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0);
87}
88
89/*******************************************************************************
90 * Setup CPU vectors for resume from deep sleep
91 ******************************************************************************/
92void tegra_pmc_cpu_setup(uint64_t reset_addr)
93{
94 uint32_t val;
95
96 tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1);
97 val = reset_addr >> 32;
98 tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF);
99}
100
101/*******************************************************************************
102 * Lock CPU vectors to restrict further writes
103 ******************************************************************************/
104void tegra_pmc_lock_cpu_vectors(void)
105{
106 uint32_t val;
107
Varun Wadekar30d89772015-07-16 10:38:11 +0530108 /* lock PMC_SECURE_SCRATCH22 */
109 val = tegra_pmc_read_32(PMC_SECURE_DISABLE2);
110 val |= PMC_SECURE_DISABLE2_WRITE22_ON;
111 tegra_pmc_write_32(PMC_SECURE_DISABLE2, val);
112
Varun Wadekarb316e242015-05-19 16:48:04 +0530113 /* lock PMC_SECURE_SCRATCH34/35 */
114 val = tegra_pmc_read_32(PMC_SECURE_DISABLE3);
115 val |= (PMC_SECURE_DISABLE3_WRITE34_ON |
116 PMC_SECURE_DISABLE3_WRITE35_ON);
117 tegra_pmc_write_32(PMC_SECURE_DISABLE3, val);
118}
119
120/*******************************************************************************
121 * Restart the system
122 ******************************************************************************/
123__dead2 void tegra_pmc_system_reset(void)
124{
125 uint32_t reg;
126
127 reg = tegra_pmc_read_32(PMC_CONFIG);
128 reg |= 0x10; /* restart */
129 tegra_pmc_write_32(PMC_CONFIG, reg);
130 wfi();
131
132 ERROR("Tegra System Reset: operation not handled.\n");
133 panic();
134}