David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
Govindraj Raja | eee28e7 | 2023-08-01 15:52:40 -0500 | [diff] [blame^] | 2 | * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 7 | #ifndef CORTEX_A75_H |
| 8 | #define CORTEX_A75_H |
| 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 11 | |
| 12 | /* Cortex-A75 MIDR */ |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 13 | #define CORTEX_A75_MIDR U(0x410fd0a0) |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 14 | |
| 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define CORTEX_A75_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 19 | #define CORTEX_A75_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 20 | |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 21 | /******************************************************************************* |
| 22 | * CPU Auxiliary Control register specific definitions. |
| 23 | ******************************************************************************/ |
| 24 | #define CORTEX_A75_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 25 | |
Antonio Nino Diaz | 96f1631 | 2019-02-11 13:34:54 +0000 | [diff] [blame] | 26 | #define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 35) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 27 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 28 | /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 29 | #define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1) |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 30 | |
Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 31 | #define CORTEX_A75_ACTLR_AMEN_BIT (ULL(1) << 4) |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * The Cortex-A75 core implements five counters, 0-4. Events 0, 1, 2, are |
| 35 | * fixed and are enabled (Group 0). Events 3 and 4 (Group 1) are |
| 36 | * programmable by programming the appropriate Event count bits in |
| 37 | * CPUAMEVTYPER<n> register and are disabled by default. Platforms may |
| 38 | * enable this with suitable programming. |
| 39 | */ |
Dimitris Papastamos | 864364a | 2018-02-27 10:55:39 +0000 | [diff] [blame] | 40 | #define CORTEX_A75_AMU_NR_COUNTERS U(5) |
| 41 | #define CORTEX_A75_AMU_GROUP0_MASK U(0x7) |
| 42 | #define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 43 | |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 44 | #ifndef __ASSEMBLER__ |
Dimitris Papastamos | d7e2e9e | 2017-12-11 11:45:35 +0000 | [diff] [blame] | 45 | #include <stdint.h> |
| 46 | |
| 47 | uint64_t cortex_a75_amu_cnt_read(int idx); |
| 48 | void cortex_a75_amu_cnt_write(int idx, uint64_t val); |
| 49 | unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); |
| 50 | unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); |
| 51 | void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); |
| 52 | void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); |
Julius Werner | 53456fc | 2019-07-09 13:49:11 -0700 | [diff] [blame] | 53 | #endif /* __ASSEMBLER__ */ |
Dimitris Papastamos | d7e2e9e | 2017-12-11 11:45:35 +0000 | [diff] [blame] | 54 | |
Antonio Nino Diaz | 9fe40fd | 2018-10-25 17:11:02 +0100 | [diff] [blame] | 55 | #endif /* CORTEX_A75_H */ |