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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -07002 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#include <assert.h>
Soren Brinkmann76fcae32016-03-06 20:16:27 -08008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <bl31/bl31.h>
11#include <common/bl_common.h>
12#include <common/debug.h>
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070013#include <drivers/arm/dcc.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <drivers/console.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/platform.h>
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070017#include <lib/mmio.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070019#include <plat_startup.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000020#include <plat_private.h>
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070021#include <zynqmp_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000022
Michal Simek53865b02021-05-27 09:42:37 +020023#include <common/fdt_fixup.h>
24#include <common/fdt_wrappers.h>
25#include <libfdt.h>
26
Soren Brinkmann76fcae32016-03-06 20:16:27 -080027static entry_point_info_t bl32_image_ep_info;
28static entry_point_info_t bl33_image_ep_info;
29
30/*
31 * Return a pointer to the 'entry_point_info' structure of the next image for
32 * the security state specified. BL33 corresponds to the non-secure image type
33 * while BL32 corresponds to the secure image type. A NULL pointer is returned
34 * if the image does not exist.
35 */
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053036struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080037{
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053038 entry_point_info_t *next_image_info;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080039
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053040 assert(sec_state_is_valid(type));
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070041 if (type == NON_SECURE) {
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053042 next_image_info = &bl33_image_ep_info;
43 } else {
44 next_image_info = &bl32_image_ep_info;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -070045 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080046
Venkatesh Yadav Abbarapuc70726f2022-05-16 17:44:33 +053047 return next_image_info;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080048}
49
50/*
Alistair Francisb8d474f2017-11-30 16:21:21 -080051 * Set the build time defaults. We want to do this when doing a JTAG boot
52 * or if we can't find any other config data.
53 */
54static inline void bl31_set_default_config(void)
55{
56 bl32_image_ep_info.pc = BL32_BASE;
57 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
58 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
59 bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
60 DISABLE_ALL_EXCEPTIONS);
61}
62
63/*
Soren Brinkmann76fcae32016-03-06 20:16:27 -080064 * Perform any BL31 specific platform actions. Here is an opportunity to copy
John Tsichritzisd653d332018-09-14 10:34:57 +010065 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they
Soren Brinkmann76fcae32016-03-06 20:16:27 -080066 * are lost (potentially). This needs to be done before the MMU is initialized
67 * so that the memory layout can be used while creating page tables.
68 */
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010069void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
70 u_register_t arg2, u_register_t arg3)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080071{
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -070072 uint64_t atf_handoff_addr;
Soren Brinkmann76fcae32016-03-06 20:16:27 -080073
Venkatesh Yadav Abbarapu0bd80de2021-12-19 21:32:00 -070074 if (ZYNQMP_CONSOLE_IS(cadence) || (ZYNQMP_CONSOLE_IS(cadence1))) {
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070075 /* Register the console to provide early debug support */
76 static console_t bl31_boot_console;
77 (void)console_cdns_register(ZYNQMP_UART_BASE,
78 zynqmp_get_uart_clk(),
79 ZYNQMP_UART_BAUDRATE,
80 &bl31_boot_console);
81 console_set_scope(&bl31_boot_console,
82 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
83 } else if (ZYNQMP_CONSOLE_IS(dcc)) {
84 /* Initialize the dcc console for debug */
Venkatesh Yadav Abbarapue7c45382022-05-19 14:49:49 +053085 int32_t rc = console_dcc_register();
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070086 if (rc == 0) {
87 panic();
88 }
Venkatesh Yadav Abbarapuccf6da72022-05-04 14:23:32 +053089 } else {
90 ERROR("BL31: No console device found.\n");
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070091 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -080092 /* Initialize the platform config for future decision making */
93 zynqmp_config_setup();
94
95 /* There are no parameters from BL2 if BL31 is a reset vector */
Antonio Nino Diaz012c8bf2018-09-24 17:16:52 +010096 assert(arg0 == 0U);
97 assert(arg1 == 0U);
Soren Brinkmann76fcae32016-03-06 20:16:27 -080098
99 /*
100 * Do initial security configuration to allow DRAM/device access. On
101 * Base ZYNQMP only DRAM security is programmable (via TrustZone), but
102 * other platforms might have more programmable security devices
103 * present.
104 */
105
Michal Simekef8f5592015-06-15 14:22:50 +0200106 /* Populate common information for BL32 and BL33 */
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800107 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
108 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800109 SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800110 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
111
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -0700112 atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6);
113
Michal Simekef8f5592015-06-15 14:22:50 +0200114 if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) {
Alistair Francisb8d474f2017-11-30 16:21:21 -0800115 bl31_set_default_config();
Michal Simekef8f5592015-06-15 14:22:50 +0200116 } else {
117 /* use parameters from FSBL */
Siva Durga Prasad Paladugu8f499722018-05-17 15:17:46 +0530118 enum fsbl_handoff ret = fsbl_atf_handover(&bl32_image_ep_info,
Venkatesh Yadav Abbarapu1463dd52020-01-07 03:25:16 -0700119 &bl33_image_ep_info,
120 atf_handoff_addr);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700121 if (ret == FSBL_HANDOFF_NO_STRUCT) {
Alistair Francisb8d474f2017-11-30 16:21:21 -0800122 bl31_set_default_config();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700123 } else if (ret != FSBL_HANDOFF_SUCCESS) {
Siva Durga Prasad Paladugu8f499722018-05-17 15:17:46 +0530124 panic();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700125 }
Michal Simekef8f5592015-06-15 14:22:50 +0200126 }
Venkatesh Yadav Abbarapu3a33f932022-05-04 14:27:56 +0530127 if (bl32_image_ep_info.pc != 0) {
Venkatesh Yadav Abbarapu621c1b22020-01-10 03:01:35 -0700128 VERBOSE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
129 }
Venkatesh Yadav Abbarapu3a33f932022-05-04 14:27:56 +0530130 if (bl33_image_ep_info.pc != 0) {
Venkatesh Yadav Abbarapu621c1b22020-01-10 03:01:35 -0700131 VERBOSE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
132 }
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800133}
134
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530135#if ZYNQMP_WDT_RESTART
136static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
137
138int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
139{
140 /* Validate 'handler' and 'id' parameters */
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700141 if (!handler || id >= MAX_INTR_EL3) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530142 return -EINVAL;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700143 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530144
145 /* Check if a handler has already been registered */
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700146 if (type_el3_interrupt_table[id]) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530147 return -EALREADY;
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700148 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530149
150 type_el3_interrupt_table[id] = handler;
151
152 return 0;
153}
154
155static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
156 void *handle, void *cookie)
157{
158 uint32_t intr_id;
159 interrupt_type_handler_t handler;
160
161 intr_id = plat_ic_get_pending_interrupt_id();
162 handler = type_el3_interrupt_table[intr_id];
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700163 if (handler != NULL) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530164 handler(intr_id, flags, handle, cookie);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700165 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530166
167 return 0;
168}
169#endif
170
Michal Simek53865b02021-05-27 09:42:37 +0200171#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
172static void prepare_dtb(void)
173{
174 void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
175 int ret;
176
177 /* Return if no device tree is detected */
178 if (fdt_check_header(dtb) != 0) {
179 NOTICE("Can't read DT at 0x%p\n", dtb);
180 return;
181 }
182
183 ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
184 if (ret < 0) {
185 ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
186 return;
187 }
188
189 if (dt_add_psci_node(dtb)) {
190 ERROR("Failed to add PSCI Device Tree node\n");
191 return;
192 }
193
194 if (dt_add_psci_cpu_enable_methods(dtb)) {
195 ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
196 return;
197 }
198
199 /* Reserve memory used by Trusted Firmware. */
200 if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
201 WARN("Failed to add reserved memory nodes to DT.\n");
202 }
203
204 ret = fdt_pack(dtb);
205 if (ret < 0) {
206 ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
207 }
208
209 clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
210 INFO("Changed device tree to advertise PSCI and reserved memories.\n");
211}
212#endif
213
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800214void bl31_platform_setup(void)
215{
Michal Simek53865b02021-05-27 09:42:37 +0200216#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
217 prepare_dtb();
218#endif
219
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800220 /* Initialize the gic cpu and distributor interfaces */
221 plat_arm_gic_driver_init();
222 plat_arm_gic_init();
223}
224
225void bl31_plat_runtime_setup(void)
226{
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530227#if ZYNQMP_WDT_RESTART
228 uint64_t flags = 0;
229 uint64_t rc;
230
231 set_interrupt_rm_flag(flags, NON_SECURE);
232 rc = register_interrupt_type_handler(INTR_TYPE_EL3,
233 rdo_el3_interrupt_handler, flags);
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700234 if (rc) {
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530235 panic();
Venkatesh Yadav Abbarapu5f115db2021-01-10 20:40:16 -0700236 }
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530237#endif
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800238}
239
240/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100241 * Perform the very early platform specific architectural setup here.
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800242 */
243void bl31_plat_arch_setup(void)
244{
245 plat_arm_interconnect_init();
246 plat_arm_interconnect_enter_coherency();
247
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100248
249 const mmap_region_t bl_regions[] = {
Michal Simek53865b02021-05-27 09:42:37 +0200250#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
251 MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
252 MT_MEMORY | MT_RW | MT_NS),
253#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100254 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
255 MT_MEMORY | MT_RW | MT_SECURE),
256 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
257 MT_CODE | MT_SECURE),
258 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
259 MT_RO_DATA | MT_SECURE),
260 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
261 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
262 MT_DEVICE | MT_RW | MT_SECURE),
263 {0}
264 };
265
Roberto Vargas344ff022018-10-19 16:44:18 +0100266 setup_page_tables(bl_regions, plat_arm_get_mmap());
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100267 enable_mmu_el3(0);
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800268}